478 lines
33 KiB
XML
478 lines
33 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="MOV_rr" title="MOV, MOVS (register-shifted register) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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</docvars>
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<heading>MOV, MOVS (register-shifted register)</heading>
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<desc>
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<brief>
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<para>Move (register-shifted register)</para>
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</brief>
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<authored>
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<para>Move (register-shifted register) copies a register-shifted register value to the destination register. It can optionally update the condition flags based on the value.</para>
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</authored>
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<encodingnotes>
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<para>Related encodings: In encoding T1, for an <field>op</field> field value that is not described above, see <xref linkend="T32.encoding_index.dpint16_2l">Data-processing (two low registers)</xref>.</para>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="8">
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<alias_list_intro>This instruction is used by the aliases </alias_list_intro>
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<aliasref aliaspageid="ASRS_MOV_rr" aliasfile="asrs_mov_rr.xml" hover="Arithmetic Shift Right" punct=", ">
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<text>ASRS (register)</text>
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<aliaspref labels="A1 (flag setting)">S == '1' && stype == '10'</aliaspref>
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<aliaspref labels="T1 (arithmetic shift right)">op == '0100' && !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
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<aliaspref labels="T2 (flag setting)">stype == '10' && S == '1'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="ASR_MOV_rr" aliasfile="asr_mov_rr.xml" hover="Arithmetic Shift Right (register)" punct=", ">
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<text>ASR (register)</text>
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<aliaspref labels="A1 (not flag setting)">S == '0' && stype == '10'</aliaspref>
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<aliaspref labels="T1 (arithmetic shift right)">op == '0100' && <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
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<aliaspref labels="T2 (not flag setting)">stype == '10' && S == '0'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="LSLS_MOV_rr" aliasfile="lsls_mov_rr.xml" hover="Logical Shift Left" punct=", ">
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<text>LSLS (register)</text>
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<aliaspref labels="A1 (flag setting)">S == '1' && stype == '00'</aliaspref>
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<aliaspref labels="T1 (logical shift left)">op == '0010' && !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
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<aliaspref labels="T2 (flag setting)">stype == '00' && S == '1'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="LSL_MOV_rr" aliasfile="lsl_mov_rr.xml" hover="Logical Shift Left (register)" punct=", ">
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<text>LSL (register)</text>
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<aliaspref labels="A1 (not flag setting)">S == '0' && stype == '00'</aliaspref>
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<aliaspref labels="T1 (logical shift left)">op == '0010' && <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
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<aliaspref labels="T2 (not flag setting)">stype == '00' && S == '0'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="LSRS_MOV_rr" aliasfile="lsrs_mov_rr.xml" hover="Logical Shift Right" punct=", ">
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<text>LSRS (register)</text>
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<aliaspref labels="A1 (flag setting)">S == '1' && stype == '01'</aliaspref>
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<aliaspref labels="T1 (logical shift right)">op == '0011' && !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
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<aliaspref labels="T2 (flag setting)">stype == '01' && S == '1'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="LSR_MOV_rr" aliasfile="lsr_mov_rr.xml" hover="Logical Shift Right (register)" punct=", ">
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<text>LSR (register)</text>
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<aliaspref labels="A1 (not flag setting)">S == '0' && stype == '01'</aliaspref>
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<aliaspref labels="T1 (logical shift right)">op == '0011' && <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
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<aliaspref labels="T2 (not flag setting)">stype == '01' && S == '0'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="RORS_MOV_rr" aliasfile="rors_mov_rr.xml" hover="Rotate Right" punct=" and ">
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<text>RORS (register)</text>
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<aliaspref labels="A1 (flag setting)">S == '1' && stype == '11'</aliaspref>
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<aliaspref labels="T1 (rotate right)">op == '0111' && !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
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<aliaspref labels="T2 (flag setting)">stype == '11' && S == '1'</aliaspref>
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</aliasref>
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<aliasref aliaspageid="ROR_MOV_rr" aliasfile="ror_mov_rr.xml" hover="Rotate Right (register)" punct=".">
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<text>ROR (register)</text>
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<aliaspref labels="A1 (not flag setting)">S == '0' && stype == '11'</aliaspref>
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<aliaspref labels="T1 (rotate right)">op == '0111' && <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliaspref>
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<aliaspref labels="T2 (not flag setting)">stype == '11' && S == '0'</aliaspref>
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</aliasref>
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<alias_list_outro>
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<text> See </text>
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<aliastablelink />
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<text> below for details of when each alias is preferred.</text>
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</alias_list_outro>
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</alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t2">T2</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="3" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/MOV_rr/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" width="2" name="opc" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="20" name="S" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rn" settings="4">
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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</box>
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<box hibit="15" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="Rs" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" settings="1">
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<c>0</c>
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</box>
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<box hibit="6" width="2" name="stype" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="MOVS_rr_A1" oneofinclass="2" oneof="8" label="Flag setting" bitdiffs="S == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="cond-setting" value="s" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="MOVS" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>1</c>
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</box>
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<asmtemplate><text>MOVS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_rm" hover="General-purpose source register (field "Rm")"><Rm></a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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</encoding>
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<encoding name="MOV_rr_A1" oneofinclass="2" oneof="8" label="Not flag setting" bitdiffs="S == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="cond-setting" value="no-s" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="MOV" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>0</c>
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</box>
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<asmtemplate><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_rm" hover="General-purpose source register (field "Rm")"><Rm></a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/MOV_rr/A1_A.txt" mylink="aarch32.instrs.MOV_rr.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm); s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);
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setflags = (S == '1'); shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);
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if d == 15 || m == 15 || s == 15 then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="3" id="iclass_t1" no_encodings="4" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="MOV" />
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</docvars>
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<iclassintro count="4"></iclassintro>
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<regdiagram form="16" psname="aarch32/instrs/MOV_rr/T1_A.txt" tworows="1">
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<box hibit="31" width="6" settings="6">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="25" width="4" name="op" usename="1" settings="1">
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<c>0</c>
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<c>x</c>
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<c>x</c>
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<c>x</c>
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</box>
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<box hibit="21" width="3" name="Rs" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="18" width="3" name="Rdm" usename="1">
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<c colspan="3"></c>
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</box>
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</regdiagram>
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<encoding name="MOV_rr_T1_ASR" oneofinclass="4" oneof="8" label="Arithmetic shift right" bitdiffs="op == 0100">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="MOV" />
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<docvar key="mnemonic-shift-type" value="MOV-asr" />
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<docvar key="shift-type" value="asr" />
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</docvars>
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<box hibit="25" width="" name="op">
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<c></c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<asmtemplate comment="Inside IT block"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, ASR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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<asmtemplate comment="Outside IT block"><text>MOVS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, ASR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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</encoding>
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<encoding name="MOV_rr_T1_LSL" oneofinclass="4" oneof="8" label="Logical shift left" bitdiffs="op == 0010">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="MOV" />
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<docvar key="mnemonic-shift-type" value="MOV-lsl" />
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<docvar key="shift-type" value="lsl" />
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</docvars>
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<box hibit="25" width="" name="op">
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<c></c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate comment="Inside IT block"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, LSL </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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<asmtemplate comment="Outside IT block"><text>MOVS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, LSL </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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</encoding>
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<encoding name="MOV_rr_T1_LSR" oneofinclass="4" oneof="8" label="Logical shift right" bitdiffs="op == 0011">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="MOV" />
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<docvar key="mnemonic-shift-type" value="MOV-lsr" />
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<docvar key="shift-type" value="lsr" />
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</docvars>
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<box hibit="25" width="" name="op">
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<c></c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate comment="Inside IT block"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, LSR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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<asmtemplate comment="Outside IT block"><text>MOVS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, LSR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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</encoding>
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<encoding name="MOV_rr_T1_ROR" oneofinclass="4" oneof="8" label="Rotate right" bitdiffs="op == 0111">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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|
<docvar key="mnemonic" value="MOV" />
|
|
<docvar key="mnemonic-shift-type" value="MOV-ror" />
|
|
<docvar key="shift-type" value="ror" />
|
|
</docvars>
|
|
<box hibit="25" width="" name="op">
|
|
<c></c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate comment="Inside IT block"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, ROR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
|
|
<asmtemplate comment="Outside IT block"><text>MOVS</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, </text><a link="sa_rdm" hover="General-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, ROR </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/MOV_rr/T1_A.txt" mylink="aarch32.instrs.MOV_rr.T1_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !(op IN {'0010', '0011', '0100', '0111'}) then SEE "Related encodings";
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdm); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rdm); s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);
|
|
setflags = !<a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>(); shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(op<2>:op<0>);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T2" oneof="3" id="iclass_t2" no_encodings="2" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/MOV_rr/T2_A.txt">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="stype" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="20" name="S" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" settings="4">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="11" width="4" name="Rd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="7" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Rs" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="MOVS_rr_T2" oneofinclass="2" oneof="8" label="Flag setting" bitdiffs="S == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="cond-setting" value="s" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="MOVS" />
|
|
</docvars>
|
|
<box hibit="20" width="1" name="S">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate comment="Outside IT block, and <Rd>, <Rm>, <shift>, <Rs> can be represented in T1"><text>MOVS.W </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_rm" hover="General-purpose source register (field "Rm")"><Rm></a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
|
|
<asmtemplate><text>MOVS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_rm" hover="General-purpose source register (field "Rm")"><Rm></a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="MOV_rr_T2" oneofinclass="2" oneof="8" label="Not flag setting" bitdiffs="S == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="cond-setting" value="no-s" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="MOV" />
|
|
</docvars>
|
|
<box hibit="20" width="1" name="S">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate comment="Inside IT block, and <Rd>, <Rm>, <shift>, <Rs> can be represented in T1"><text>MOV</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>.W </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_rm" hover="General-purpose source register (field "Rm")"><Rm></a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
|
|
<asmtemplate><text>MOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_rm" hover="General-purpose source register (field "Rm")"><Rm></a><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> </text><a link="sa_rs" hover="General-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/MOV_rr/T2_A.txt" mylink="aarch32.instrs.MOV_rr.T2_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm); s = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rs);
|
|
setflags = (S == '1'); shift_t = <a link="impl-aarch32.DecodeRegShift.1" file="shared_pseudocode.xml" hover="function: SRType DecodeRegShift(bits(2) srtype)">DecodeRegShift</a>(stype);
|
|
if d == 15 || m == 15 || s == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="MOV_rr_A1, MOV_rr_T1_LSL, MOV_rr_T2" symboldefcount="1">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="MOV_rr_A1, MOV_rr_T1_LSL, MOV_rr_T2" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="MOV_rr_T1_LSL" symboldefcount="1">
|
|
<symbol link="sa_rdm"><Rdm></symbol>
|
|
<account encodedin="Rdm">
|
|
<intro>
|
|
<para>Is the general-purpose source register and the destination register, encoded in the "Rdm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="MOV_rr_A1, MOV_rr_T2" symboldefcount="1">
|
|
<symbol link="sa_rd"><Rd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="MOV_rr_A1, MOV_rr_T2" symboldefcount="1">
|
|
<symbol link="sa_rm"><Rm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the general-purpose source register, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="MOV_rr_A1, MOV_rr_T2" symboldefcount="1">
|
|
<symbol link="sa_shift"><shift></symbol>
|
|
<definition encodedin="stype">
|
|
<intro>Is the type of shift to be applied to the second source register, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">stype</entry>
|
|
<entry class="symbol"><shift></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">LSL</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">LSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">ASR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">ROR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="MOV_rr_A1, MOV_rr_T1_LSL, MOV_rr_T2" symboldefcount="1">
|
|
<symbol link="sa_rs"><Rs></symbol>
|
|
<account encodedin="Rs">
|
|
<intro>
|
|
<para>Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/MOV_rr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
shift_n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[s]<7:0>);
|
|
(result, carry) = <a link="impl-aarch32.Shift_C.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) Shift_C(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift_C</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;
|
|
if setflags then
|
|
PSTATE.N = result<31>;
|
|
PSTATE.Z = <a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result);
|
|
PSTATE.C = carry;
|
|
// PSTATE.V unchanged</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|