MOV, MOVS (register-shifted register) Move (register-shifted register) Move (register-shifted register) copies a register-shifted register value to the destination register. It can optionally update the condition flags based on the value. Related encodings: In encoding T1, for an op field value that is not described above, see Data-processing (two low registers). For more information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination: The execution time of this instruction is independent of:The values of the data supplied in any of its registers.The values of the NZCV flags. The response of this instruction to asynchronous exceptions does not vary based on:The values of the data supplied in any of its registers.The values of the NZCV flags. This instruction is used by the aliases ASRS (register) S == '1' && stype == '10' op == '0100' && !InITBlock() stype == '10' && S == '1' ASR (register) S == '0' && stype == '10' op == '0100' && InITBlock() stype == '10' && S == '0' LSLS (register) S == '1' && stype == '00' op == '0010' && !InITBlock() stype == '00' && S == '1' LSL (register) S == '0' && stype == '00' op == '0010' && InITBlock() stype == '00' && S == '0' LSRS (register) S == '1' && stype == '01' op == '0011' && !InITBlock() stype == '01' && S == '1' LSR (register) S == '0' && stype == '01' op == '0011' && InITBlock() stype == '01' && S == '0' RORS (register) S == '1' && stype == '11' op == '0111' && !InITBlock() stype == '11' && S == '1' ROR (register) S == '0' && stype == '11' op == '0111' && InITBlock() stype == '11' && S == '0' See below for details of when each alias is preferred. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) . != 1111 0 0 0 1 1 0 1 (0) (0) (0) (0) 0 1 1 MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> 0 MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> d = UInt(Rd); m = UInt(Rm); s = UInt(Rs); setflags = (S == '1'); shift_t = DecodeRegShift(stype); if d == 15 || m == 15 || s == 15 then UNPREDICTABLE; 0 1 0 0 0 0 0 x x x 1 0 0 MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> MOVS{<q>} <Rdm>, <Rdm>, ASR <Rs> 0 1 0 MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> MOVS{<q>} <Rdm>, <Rdm>, LSL <Rs> 0 1 1 MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> MOVS{<q>} <Rdm>, <Rdm>, LSR <Rs> 1 1 1 MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> MOVS{<q>} <Rdm>, <Rdm>, ROR <Rs> if !(op IN {'0010', '0011', '0100', '0111'}) then SEE "Related encodings"; d = UInt(Rdm); m = UInt(Rdm); s = UInt(Rs); setflags = !InITBlock(); shift_t = DecodeRegShift(op<2>:op<0>); 1 1 1 1 1 0 1 0 0 1 1 1 1 0 0 0 0 1 MOVS.W <Rd>, <Rm>, <shift> <Rs> MOVS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> 0 MOV<c>.W <Rd>, <Rm>, <shift> <Rs> MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> d = UInt(Rd); m = UInt(Rm); s = UInt(Rs); setflags = (S == '1'); shift_t = DecodeRegShift(stype); if d == 15 || m == 15 || s == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13 <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rdm> Is the general-purpose source register and the destination register, encoded in the "Rdm" field. <Rd> Is the general-purpose destination register, encoded in the "Rd" field. <Rm> Is the general-purpose source register, encoded in the "Rm" field. <shift> Is the type of shift to be applied to the second source register, stype <shift> 00 LSL 01 LSR 10 ASR 11 ROR <Rs> Is the general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field. Alias Conditions if ConditionPassed() then EncodingSpecificOperations(); shift_n = UInt(R[s]<7:0>); (result, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C); R[d] = result; if setflags then PSTATE.N = result<31>; PSTATE.Z = IsZeroBit(result); PSTATE.C = carry; // PSTATE.V unchanged