388 lines
20 KiB
XML
388 lines
20 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="B" title="B -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="B" />
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</docvars>
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<heading>B</heading>
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<desc>
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<brief>
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<para>Branch</para>
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</brief>
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<authored>
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<para>Branch causes a branch to a target address.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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<para>Related encodings: <xref linkend="T32.encoding_index.bcrtrl">Branches and miscellaneous control</xref>.</para>
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</encodingnotes>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="5">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>, </txt>
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<a href="#iclass_t2">T2</a>
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<txt>, </txt>
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<a href="#iclass_t3">T3</a>
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<txt> and </txt>
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<a href="#iclass_t4">T4</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="5" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="B" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/B/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" name="H" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" width="24" name="imm24" usename="1">
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<c colspan="24"></c>
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</box>
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</regdiagram>
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<encoding name="B_A1" oneofinclass="1" oneof="5" label="A1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="B" />
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</docvars>
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<asmtemplate><text>B</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_label_4" hover="The label of instruction that is to be branched to"><label></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/B/A1_A.txt" mylink="aarch32.instrs.B.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm24:'00', 32);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="5" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="B" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16" psname="aarch32/instrs/B/T1_A.txt" tworows="1">
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<box hibit="31" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="27" width="4" name="cond" usename="1" settings="4" constraint="!= 111x">
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<c colspan="4">!= 111x</c>
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</box>
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<box hibit="23" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="B_T1" oneofinclass="1" oneof="5" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="B" />
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</docvars>
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<asmtemplate comment="Not permitted in IT block"><text>B</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_label" hover="The label of instruction that is to be branched to"><label></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/B/T1_A.txt" mylink="aarch32.instrs.B.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if cond == '1110' then SEE "UDF";
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if cond == '1111' then SEE "SVC";
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imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm8:'0', 32);
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if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T2" oneof="5" id="iclass_t2" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="B" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16" psname="aarch32/instrs/B/T2_A.txt">
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<box hibit="31" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="26" width="11" name="imm11" usename="1">
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<c colspan="11"></c>
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</box>
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</regdiagram>
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<encoding name="B_T2" oneofinclass="1" oneof="5" label="T2">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="B" />
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</docvars>
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<asmtemplate comment="Outside or last in IT block"><text>B</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_label_1" hover="The label of instruction that is to be branched to"><label></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/B/T2_A.txt" mylink="aarch32.instrs.B.T2_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm11:'0', 32);
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if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() && !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T3" oneof="5" id="iclass_t3" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T3" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="B" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/B/T3_A.txt" tworows="1">
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<box hibit="31" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="26" name="S" usename="1">
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<c></c>
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</box>
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<box hibit="25" width="4" name="cond" usename="1" settings="4" constraint="!= 111x">
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<c colspan="4">!= 111x</c>
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</box>
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<box hibit="21" width="6" name="imm6" usename="1">
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<c colspan="6"></c>
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</box>
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<box hibit="15" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="13" name="J1" usename="1">
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<c></c>
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</box>
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<box hibit="12" settings="1">
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<c>0</c>
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</box>
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<box hibit="11" name="J2" usename="1">
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<c></c>
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</box>
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<box hibit="10" width="11" name="imm11" usename="1">
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<c colspan="11"></c>
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</box>
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</regdiagram>
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<encoding name="B_T3" oneofinclass="1" oneof="5" label="T3">
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<docvars>
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<docvar key="armarmheading" value="T3" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="B" />
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</docvars>
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<asmtemplate comment="Not permitted in IT block, and <label> can be represented in T1"><text>B</text><a link="sa_c_2" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>.W </text><a link="sa_label_2" hover="The label of instruction that is to be branched to"><label></a></asmtemplate>
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<asmtemplate comment="Not permitted in IT block"><text>B</text><a link="sa_c_2" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_label_2" hover="The label of instruction that is to be branched to"><label></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/B/T3_A.txt" mylink="aarch32.instrs.B.T3_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if cond<3:1> == '111' then SEE "Related encodings";
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imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(S:J2:J1:imm6:imm11:'0', 32);
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if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T4" oneof="5" id="iclass_t4" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T4" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="B" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/B/T4_A.txt">
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<box hibit="31" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="26" name="S" usename="1">
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<c></c>
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</box>
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<box hibit="25" width="10" name="imm10" usename="1">
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<c colspan="10"></c>
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</box>
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<box hibit="15" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="13" name="J1" usename="1">
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<c></c>
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</box>
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<box hibit="12" settings="1">
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<c>1</c>
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</box>
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<box hibit="11" name="J2" usename="1">
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<c></c>
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</box>
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<box hibit="10" width="11" name="imm11" usename="1">
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<c colspan="11"></c>
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</box>
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</regdiagram>
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<encoding name="B_T4" oneofinclass="1" oneof="5" label="T4">
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<docvars>
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<docvar key="armarmheading" value="T4" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="B" />
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</docvars>
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<asmtemplate comment="<label> can be represented in T2"><text>B</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>.W </text><a link="sa_label_3" hover="The label of instruction that is to be branched to"><label></a></asmtemplate>
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<asmtemplate><text>B</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_label_3" hover="The label of instruction that is to be branched to"><label></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/B/T4_A.txt" mylink="aarch32.instrs.B.T4_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(S:I1:I2:imm10:imm11:'0', 32);
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if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() && !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="B_A1, B_T2, B_T4" symboldefcount="1">
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<symbol link="sa_c_1"><c></symbol>
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<account encodedin="">
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<intro>
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<para>For encoding A1, T2 and T4: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="B_T1" symboldefcount="2">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must not be <value>AL</value> or omitted.</para>
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</intro>
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</account>
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||
</explanation>
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<explanation enclist="B_T3" symboldefcount="3">
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<symbol link="sa_c_2"><c></symbol>
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||
<account encodedin="">
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||
<docvars>
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||
<docvar key="armarmheading" value="T3" />
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||
<docvar key="isa" value="T32" />
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||
</docvars>
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||
<intro>
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<para>For encoding T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. <syntax><c></syntax> must not be <value>AL</value> or omitted.</para>
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</intro>
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||
</account>
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</explanation>
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<explanation enclist="B_A1, B_T1, B_T2, B_T3, B_T4" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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||
<account encodedin="">
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||
<intro>
|
||
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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||
</intro>
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||
</account>
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||
</explanation>
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||
<explanation enclist="B_A1" symboldefcount="1">
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<symbol link="sa_label_4"><label></symbol>
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||
<account encodedin="imm24">
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||
<docvars>
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||
<docvar key="armarmheading" value="A1" />
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||
<docvar key="isa" value="A32" />
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||
</docvars>
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||
<intro>
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<para>For encoding A1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>B</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset.</para>
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<para>Permitted offsets are multiples of 4 in the range –33554432 to 33554428.</para>
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||
</intro>
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||
</account>
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||
</explanation>
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||
<explanation enclist="B_T1" symboldefcount="2">
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||
<symbol link="sa_label"><label></symbol>
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||
<account encodedin="imm8">
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||
<docvars>
|
||
<docvar key="armarmheading" value="T1" />
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||
<docvar key="isa" value="T32" />
|
||
</docvars>
|
||
<intro>
|
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<para>For encoding T1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>B</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset. Permitted offsets are even numbers in the range –256 to 254.</para>
|
||
</intro>
|
||
</account>
|
||
</explanation>
|
||
<explanation enclist="B_T2" symboldefcount="3">
|
||
<symbol link="sa_label_1"><label></symbol>
|
||
<account encodedin="imm11">
|
||
<docvars>
|
||
<docvar key="armarmheading" value="T2" />
|
||
<docvar key="isa" value="T32" />
|
||
</docvars>
|
||
<intro>
|
||
<para>For encoding T2: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>B</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset. Permitted offsets are even numbers in the range –2048 to 2046.</para>
|
||
</intro>
|
||
</account>
|
||
</explanation>
|
||
<explanation enclist="B_T3" symboldefcount="4">
|
||
<symbol link="sa_label_2"><label></symbol>
|
||
<account encodedin="S:J2:J1:imm6:imm11">
|
||
<docvars>
|
||
<docvar key="armarmheading" value="T3" />
|
||
<docvar key="isa" value="T32" />
|
||
</docvars>
|
||
<intro>
|
||
<para>For encoding T3: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>B</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset.</para>
|
||
<para>Permitted offsets are even numbers in the range –1048576 to 1048574.</para>
|
||
</intro>
|
||
</account>
|
||
</explanation>
|
||
<explanation enclist="B_T4" symboldefcount="5">
|
||
<symbol link="sa_label_3"><label></symbol>
|
||
<account encodedin="">
|
||
<docvars>
|
||
<docvar key="armarmheading" value="T4" />
|
||
<docvar key="isa" value="T32" />
|
||
</docvars>
|
||
<intro>
|
||
<para>For encoding T4: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the <instruction>B</instruction> instruction to this label, then selects an encoding that sets <field>imm32</field> to that offset.</para>
|
||
<para>Permitted offsets are even numbers in the range –16777216 to 16777214.</para>
|
||
</intro>
|
||
</account>
|
||
</explanation>
|
||
</explanations>
|
||
<ps_section howmany="1">
|
||
<ps name="aarch32/instrs/B/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
||
EncodingSpecificOperations();
|
||
<a link="impl-aarch32.BranchWritePC.2" file="shared_pseudocode.xml" hover="function: BranchWritePC(bits(32) address_in, BranchType branch_type)">BranchWritePC</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> + imm32, <a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>);</pstext>
|
||
</ps>
|
||
</ps_section>
|
||
</instructionsection>
|