B Branch Branch causes a branch to a target address. For more information about the constrained unpredictable behavior, see Architectural Constraints on UNPREDICTABLE behaviors. Related encodings: Branches and miscellaneous control. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 , T3 and T4 ) . != 1111 1 0 1 0 B{<c>}{<q>} <label> imm32 = SignExtend(imm24:'00', 32); 1 1 0 1 != 111x B<c>{<q>} <label> if cond == '1110' then SEE "UDF"; if cond == '1111' then SEE "SVC"; imm32 = SignExtend(imm8:'0', 32); if InITBlock() then UNPREDICTABLE; 1 1 1 0 0 B{<c>}{<q>} <label> imm32 = SignExtend(imm11:'0', 32); if InITBlock() && !LastInITBlock() then UNPREDICTABLE; 1 1 1 1 0 != 111x 1 0 0 B<c>.W <label> B<c>{<q>} <label> if cond<3:1> == '111' then SEE "Related encodings"; imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32); if InITBlock() then UNPREDICTABLE; 1 1 1 1 0 1 0 1 B{<c>}.W <label> B{<c>}{<q>} <label> I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S); imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); if InITBlock() && !LastInITBlock() then UNPREDICTABLE; <c> For encoding A1, T2 and T4: see Standard assembler syntax fields. <c> For encoding T1: see Standard assembler syntax fields. Must not be AL or omitted. <c> For encoding T3: see Standard assembler syntax fields. <c> must not be AL or omitted. <q> See Standard assembler syntax fields. <label> For encoding A1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are multiples of 4 in the range –33554432 to 33554428. <label> For encoding T1: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –256 to 254. <label> For encoding T2: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –2048 to 2046. <label> For encoding T3: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –1048576 to 1048574. <label> For encoding T4: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –16777216 to 16777214. if ConditionPassed() then EncodingSpecificOperations(); BranchWritePC(PC + imm32, BranchType_DIR);