871 lines
56 KiB
XML
871 lines
56 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="VST1_1" title="VST1 (single element from one lane) -- AArch32" type="instruction">
|
|
<docvars>
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<heading>VST1 (single element from one lane)</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Store single element from one lane of one register</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Store single element from one lane of one register stores one element to memory from one element of a register. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
|
|
<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
|
|
</authored>
|
|
<encodingnotes>
|
|
<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
|
|
</encodingnotes>
|
|
<syntaxnotes>
|
|
<para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
|
|
</syntaxnotes>
|
|
</desc>
|
|
<operationalnotes>
|
|
<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
|
|
</operationalnotes>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<classesintro count="6">
|
|
<txt>It has encodings from the following instruction sets:</txt>
|
|
<txt> A32 (</txt>
|
|
<a href="#iclass_a1">A1</a>
|
|
<txt>, </txt>
|
|
<a href="#iclass_a2">A2</a>
|
|
<txt> and </txt>
|
|
<a href="#iclass_a3">A3</a>
|
|
<txt>)</txt>
|
|
<txt> and </txt>
|
|
<txt> T32 (</txt>
|
|
<a href="#iclass_t1">T1</a>
|
|
<txt>, </txt>
|
|
<a href="#iclass_t2">T2</a>
|
|
<txt> and </txt>
|
|
<a href="#iclass_t3">T3</a>
|
|
<txt>)</txt>
|
|
<txt>.</txt>
|
|
</classesintro>
|
|
<iclass name="A1" oneof="6" id="iclass_a1" no_encodings="3" isa="A32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<iclassintro count="3"></iclassintro>
|
|
<regdiagram form="32" psname="aarch32/instrs/VST1_1/T1A1_A.txt" tworows="1">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="L" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="size" usename="1" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="N" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="4" name="index_align" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VST1_1_A1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_A1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]!</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_A1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="address-offset" value="reg-offset" />
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>N</c>
|
|
<c>N</c>
|
|
<c></c>
|
|
<c>N</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field "Rm")"><Rm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VST1_1/T1A1_A.txt" mylink="aarch32.instrs.VST1_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' then UNDEFINED;
|
|
if index_align<0> != '0' then UNDEFINED;
|
|
ebytes = 1; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align<3:1>); alignment = 1;
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
|
wback = (m != 15); register_index = (m != 15 && m != 13);
|
|
if n == 15 then UNPREDICTABLE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="A2" oneof="6" id="iclass_a2" no_encodings="3" isa="A32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<iclassintro count="3"></iclassintro>
|
|
<regdiagram form="32" psname="aarch32/instrs/VST1_1/T2A2_A.txt" tworows="1">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="L" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="size" usename="1" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="N" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="4" name="index_align" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VST1_1_A2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="armarmheading" value="A2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_A2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="armarmheading" value="A2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]!</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_A2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="address-offset" value="reg-offset" />
|
|
<docvar key="armarmheading" value="A2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>N</c>
|
|
<c>N</c>
|
|
<c></c>
|
|
<c>N</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field "Rm")"><Rm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VST1_1/T2A2_A.txt" mylink="aarch32.instrs.VST1_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' then UNDEFINED;
|
|
if index_align<1> != '0' then UNDEFINED;
|
|
ebytes = 2; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align<3:2>);
|
|
alignment = if index_align<0> == '0' then 1 else 2;
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
|
wback = (m != 15); register_index = (m != 15 && m != 13);
|
|
if n == 15 then UNPREDICTABLE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="A3" oneof="6" id="iclass_a3" no_encodings="3" isa="A32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<iclassintro count="3"></iclassintro>
|
|
<regdiagram form="32" psname="aarch32/instrs/VST1_1/T3A3_A.txt" tworows="1">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="L" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="size" usename="1" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="N" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="4" name="index_align" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VST1_1_A3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="armarmheading" value="A3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_A3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="armarmheading" value="A3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]!</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_A3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="address-offset" value="reg-offset" />
|
|
<docvar key="armarmheading" value="A3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>N</c>
|
|
<c>N</c>
|
|
<c></c>
|
|
<c>N</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field "Rm")"><Rm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VST1_1/T3A3_A.txt" mylink="aarch32.instrs.VST1_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' then UNDEFINED;
|
|
if index_align<2> != '0' then UNDEFINED;
|
|
if index_align<1:0> != '00' && index_align<1:0> != '11' then UNDEFINED;
|
|
ebytes = 4; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align<3>);
|
|
alignment = if index_align<1:0> == '00' then 1 else 4;
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
|
wback = (m != 15); register_index = (m != 15 && m != 13);
|
|
if n == 15 then UNPREDICTABLE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T1" oneof="6" id="iclass_t1" no_encodings="3" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<iclassintro count="3"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VST1_1/T1A1_A.txt" tworows="1">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="L" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="size" usename="1" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="N" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="4" name="index_align" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VST1_1_T1_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_T1_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]!</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_T1_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="address-offset" value="reg-offset" />
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>N</c>
|
|
<c>N</c>
|
|
<c></c>
|
|
<c>N</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field "Rm")"><Rm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VST1_1/T1A1_A.txt" mylink="aarch32.instrs.VST1_1.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' then UNDEFINED;
|
|
if index_align<0> != '0' then UNDEFINED;
|
|
ebytes = 1; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align<3:1>); alignment = 1;
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
|
wback = (m != 15); register_index = (m != 15 && m != 13);
|
|
if n == 15 then UNPREDICTABLE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T2" oneof="6" id="iclass_t2" no_encodings="3" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<iclassintro count="3"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VST1_1/T2A2_A.txt" tworows="1">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="L" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="size" usename="1" settings="2">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="N" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="4" name="index_align" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VST1_1_T2_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_T2_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]!</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_T2_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="address-offset" value="reg-offset" />
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>N</c>
|
|
<c>N</c>
|
|
<c></c>
|
|
<c>N</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field "Rm")"><Rm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VST1_1/T2A2_A.txt" mylink="aarch32.instrs.VST1_1.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' then UNDEFINED;
|
|
if index_align<1> != '0' then UNDEFINED;
|
|
ebytes = 2; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align<3:2>);
|
|
alignment = if index_align<0> == '0' then 1 else 2;
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
|
wback = (m != 15); register_index = (m != 15 && m != 13);
|
|
if n == 15 then UNPREDICTABLE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T3" oneof="6" id="iclass_t3" no_encodings="3" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<iclassintro count="3"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VST1_1/T3A3_A.txt" tworows="1">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="L" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" name="size" usename="1" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="N" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="4" name="index_align" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Rm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VST1_1_T3_nowb" oneofinclass="3" oneof="18" label="Offset" bitdiffs="Rm == 1111">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_T3_posti" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm == 1101">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>]!</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VST1_1_T3_postr" oneofinclass="3" oneof="18" label="Post-indexed" bitdiffs="Rm != 11x1">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="address-offset" value="reg-offset" />
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VST1" />
|
|
</docvars>
|
|
<box hibit="3" width="4" name="Rm">
|
|
<c>N</c>
|
|
<c>N</c>
|
|
<c></c>
|
|
<c>N</c>
|
|
</box>
|
|
<asmtemplate><text>VST1</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32]"><size></a><text> </text><a link="sa_list" hover="List containing the single 64-bit SIMD&FP register holding element (field "D:Vd")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>:</text><a link="sa_align" hover="When {syntax{<size>}} == 8, {syntax{<align>}} must be omitted, otherwise it is the optional alignment (field "index_align<0>")"><align></a><text>}</text><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field "Rm")"><Rm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VST1_1/T3A3_A.txt" mylink="aarch32.instrs.VST1_1.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' then UNDEFINED;
|
|
if index_align<2> != '0' then UNDEFINED;
|
|
if index_align<1:0> != '00' && index_align<1:0> != '11' then UNDEFINED;
|
|
ebytes = 4; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(index_align<3>);
|
|
alignment = if index_align<1:0> == '00' then 1 else 4;
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
|
wback = (m != 15); register_index = (m != 15 && m != 13);
|
|
if n == 15 then UNPREDICTABLE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb" symboldefcount="1">
|
|
<symbol link="sa_c_1"><c></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1, A2 and A3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="2">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb, VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb, VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="1">
|
|
<symbol link="sa_size"><size></symbol>
|
|
<definition encodedin="size">
|
|
<intro>Is the data size, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">size</entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb, VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="1">
|
|
<symbol link="sa_list"><list></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is a list containing the single 64-bit name of the SIMD&FP register holding the element.</para>
|
|
<para>The list must be <syntax>{ <Dd>[<index>] }</syntax>.</para>
|
|
<para>The register <syntax><Dd></syntax> is encoded in the "D:Vd" field.</para>
|
|
<para>The permitted values and encoding of <syntax><index></syntax> depend on <syntax><size></syntax>:</para>
|
|
<list type="param">
|
|
<listitem>
|
|
<param><syntax><size></syntax> == 8</param><content><syntax><index></syntax> is in the range 0 to 7, encoded in the "index_align<3:1>" field.</content>
|
|
</listitem>
|
|
<listitem>
|
|
<param><syntax><size></syntax> == 16</param><content><syntax><index></syntax> is in the range 0 to 3, encoded in the "index_align<3:2>" field.</content>
|
|
</listitem>
|
|
<listitem>
|
|
<param><syntax><size></syntax> == 32</param><content><syntax><index></syntax> is 0 or 1, encoded in the "index_align<3>" field.</content>
|
|
</listitem>
|
|
</list>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb, VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="1">
|
|
<symbol link="sa_rn"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the general-purpose base register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VST1_1_A1_nowb, VST1_1_A2_nowb, VST1_1_A3_nowb, VST1_1_T1_nowb, VST1_1_T2_nowb, VST1_1_T3_nowb" symboldefcount="1">
|
|
<symbol link="sa_align"><align></symbol>
|
|
<account encodedin="index_align<0>">
|
|
<intro>
|
|
<para>When <syntax><size></syntax> == 8, <syntax><align></syntax> must be omitted, otherwise it is the optional alignment.</para>
|
|
<para>Whenever <syntax><align></syntax> is omitted, the standard alignment is used, see <xref linkend="Chdijihg">Unaligned data access</xref>, and the encoding depends on <syntax><size></syntax>:</para>
|
|
<list type="param">
|
|
<listitem>
|
|
<param><syntax><size></syntax> == 8</param><content>Encoded in the "index_align<0>" field as <binarynumber>0</binarynumber>.</content>
|
|
</listitem>
|
|
<listitem>
|
|
<param><syntax><size></syntax> == 16</param><content>Encoded in the "index_align<1:0>" field as <binarynumber>0b00</binarynumber>.</content>
|
|
</listitem>
|
|
<listitem>
|
|
<param><syntax><size></syntax> == 32</param><content>Encoded in the "index_align<2:0>" field as <binarynumber>0b000</binarynumber>.</content>
|
|
</listitem>
|
|
</list>
|
|
<para>Whenever <syntax><align></syntax> is present, the permitted values and encoding depend on <syntax><size></syntax>:</para>
|
|
<list type="param">
|
|
<listitem>
|
|
<param><syntax><size></syntax> == 16</param><content><syntax><align></syntax> is 16, meaning 16-bit alignment, encoded in the "index_align<1:0>" field as <binarynumber>0b01</binarynumber>.</content>
|
|
</listitem>
|
|
<listitem>
|
|
<param><syntax><size></syntax> == 32</param><content><syntax><align></syntax> is 32, meaning 32-bit alignment, encoded in the "index_align<2:0>" field as <binarynumber>0b011</binarynumber>.</content>
|
|
</listitem>
|
|
</list>
|
|
<para><value>:</value> is the preferred separator before the <syntax><align></syntax> value, but the alignment can be specified as <value>@<align></value>, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VST1_1_A1_postr, VST1_1_A2_postr, VST1_1_A3_postr, VST1_1_T1_postr, VST1_1_T2_postr, VST1_1_T3_postr" symboldefcount="1">
|
|
<symbol link="sa_rm"><Rm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VST1_1/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
<a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
|
|
|
|
address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
|
|
|
|
boolean nontemporal = FALSE;
|
|
boolean tagchecked = FALSE;
|
|
<a link="AccessDescriptor" file="shared_pseudocode.xml" hover="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a link="impl-shared.CreateAccDescASIMD.3" file="shared_pseudocode.xml" hover="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(<a link="MemOp_STORE" file="shared_pseudocode.xml" hover="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>, nontemporal, tagchecked);
|
|
if !<a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, alignment) then
|
|
<a link="AArch32.Abort.2" file="shared_pseudocode.xml" hover="function: AArch32.Abort(bits(32) vaddress, FaultRecord fault)">AArch32.Abort</a>(address, <a link="impl-shared.AlignmentFault.1" file="shared_pseudocode.xml" hover="function: FaultRecord AlignmentFault(AccessDescriptor accdesc)">AlignmentFault</a>(accdesc));
|
|
|
|
<a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,ebytes] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d],index,8*ebytes];
|
|
if wback then
|
|
if register_index then
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];
|
|
else
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + ebytes;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|