732 lines
41 KiB
XML
732 lines
41 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VSEL" title="VSELEQ, VSELGE, VSELGT, VSELVS -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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</docvars>
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<heading>VSELEQ, VSELGE, VSELGT, VSELVS</heading>
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<desc>
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<brief>
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<para>Floating-point conditional select</para>
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</brief>
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<authored>
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<para>Floating-point conditional select allows the destination register to take the value in either one or the other source register according to the condition codes in the <xref linkend="CJAGBHBH">APSR</xref>.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="12" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="12"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VSEL/A1_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="cc" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
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<c colspan="2">!= 00</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" settings="1">
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<c>0</c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VSELEQ_A1_H" oneofinclass="12" oneof="24" label="Equal, half-precision scalar" bitdiffs="cc == 00 && size == 01">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="halfprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELEQ" />
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<docvar key="mnemonic-fpdatasize" value="VSELEQ-halfprec" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="21" width="2" name="cc">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELEQ.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VSELEQ_A1_S" oneofinclass="12" oneof="24" label="Equal, single-precision scalar" bitdiffs="cc == 00 && size == 10">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELEQ" />
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<docvar key="mnemonic-fpdatasize" value="VSELEQ-singleprec" />
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</docvars>
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<box hibit="21" width="2" name="cc">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELEQ.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VSELEQ_A1_D" oneofinclass="12" oneof="24" label="Equal, double-precision scalar" bitdiffs="cc == 00 && size == 11">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELEQ" />
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<docvar key="mnemonic-fpdatasize" value="VSELEQ-doubleprec" />
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</docvars>
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<box hibit="21" width="2" name="cc">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELEQ.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<encoding name="VSELGE_A1_H" oneofinclass="12" oneof="24" label="Greater than or Equal, half-precision scalar" bitdiffs="cc == 10 && size == 01">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="halfprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELGE" />
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<docvar key="mnemonic-fpdatasize" value="VSELGE-halfprec" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="21" width="2" name="cc">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELGE.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VSELGE_A1_S" oneofinclass="12" oneof="24" label="Greater than or Equal, single-precision scalar" bitdiffs="cc == 10 && size == 10">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELGE" />
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<docvar key="mnemonic-fpdatasize" value="VSELGE-singleprec" />
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</docvars>
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<box hibit="21" width="2" name="cc">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELGE.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VSELGE_A1_D" oneofinclass="12" oneof="24" label="Greater than or Equal, double-precision scalar" bitdiffs="cc == 10 && size == 11">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELGE" />
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<docvar key="mnemonic-fpdatasize" value="VSELGE-doubleprec" />
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</docvars>
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<box hibit="21" width="2" name="cc">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELGE.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<encoding name="VSELGT_A1_H" oneofinclass="12" oneof="24" label="Greater than, half-precision scalar" bitdiffs="cc == 11 && size == 01">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="halfprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELGT" />
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<docvar key="mnemonic-fpdatasize" value="VSELGT-halfprec" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="21" width="2" name="cc">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELGT.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VSELGT_A1_S" oneofinclass="12" oneof="24" label="Greater than, single-precision scalar" bitdiffs="cc == 11 && size == 10">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELGT" />
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<docvar key="mnemonic-fpdatasize" value="VSELGT-singleprec" />
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</docvars>
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<box hibit="21" width="2" name="cc">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELGT.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VSELGT_A1_D" oneofinclass="12" oneof="24" label="Greater than, double-precision scalar" bitdiffs="cc == 11 && size == 11">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELGT" />
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<docvar key="mnemonic-fpdatasize" value="VSELGT-doubleprec" />
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</docvars>
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<box hibit="21" width="2" name="cc">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELGT.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<encoding name="VSELVS_A1_H" oneofinclass="12" oneof="24" label="Unordered, half-precision scalar" bitdiffs="cc == 01 && size == 01">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="halfprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELVS" />
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<docvar key="mnemonic-fpdatasize" value="VSELVS-halfprec" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="21" width="2" name="cc">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELVS.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VSELVS_A1_S" oneofinclass="12" oneof="24" label="Unordered, single-precision scalar" bitdiffs="cc == 01 && size == 10">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELVS" />
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<docvar key="mnemonic-fpdatasize" value="VSELVS-singleprec" />
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</docvars>
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<box hibit="21" width="2" name="cc">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELVS.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VSELVS_A1_D" oneofinclass="12" oneof="24" label="Unordered, double-precision scalar" bitdiffs="cc == 01 && size == 11">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VSELVS" />
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<docvar key="mnemonic-fpdatasize" value="VSELVS-doubleprec" />
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</docvars>
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<box hibit="21" width="2" name="cc">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate comment="Cannot be conditional"><text>VSELVS.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VSEL/A1_A.txt" mylink="aarch32.instrs.VSEL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '00' || (size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
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integer esize;
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integer d;
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integer n;
|
|
integer m;
|
|
case size of
|
|
when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
|
|
when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
|
|
when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
|
|
cond = cc:(cc<1> EOR cc<0>):'0';</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="12" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<iclassintro count="12"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VSEL/T1_A.txt" tworows="1">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" name="cc" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Vn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size" usename="1" settings="2" constraint="!= 00">
|
|
<c colspan="2">!= 00</c>
|
|
</box>
|
|
<box hibit="7" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="6" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Vm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VSELEQ_T1_H" oneofinclass="12" oneof="24" label="Equal, half-precision scalar" bitdiffs="cc == 00 && size == 01">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="halfprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELEQ" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELEQ-halfprec" />
|
|
</docvars>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
|
|
</arch_variants>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELEQ.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VSELEQ_T1_S" oneofinclass="12" oneof="24" label="Equal, single-precision scalar" bitdiffs="cc == 00 && size == 10">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="singleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELEQ" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELEQ-singleprec" />
|
|
</docvars>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELEQ.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VSELEQ_T1_D" oneofinclass="12" oneof="24" label="Equal, double-precision scalar" bitdiffs="cc == 00 && size == 11">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="doubleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELEQ" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELEQ-doubleprec" />
|
|
</docvars>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELEQ.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VSELGE_T1_H" oneofinclass="12" oneof="24" label="Greater than or Equal, half-precision scalar" bitdiffs="cc == 10 && size == 01">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="halfprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELGE" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELGE-halfprec" />
|
|
</docvars>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
|
|
</arch_variants>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELGE.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VSELGE_T1_S" oneofinclass="12" oneof="24" label="Greater than or Equal, single-precision scalar" bitdiffs="cc == 10 && size == 10">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="singleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELGE" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELGE-singleprec" />
|
|
</docvars>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELGE.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VSELGE_T1_D" oneofinclass="12" oneof="24" label="Greater than or Equal, double-precision scalar" bitdiffs="cc == 10 && size == 11">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="doubleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELGE" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELGE-doubleprec" />
|
|
</docvars>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELGE.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VSELGT_T1_H" oneofinclass="12" oneof="24" label="Greater than, half-precision scalar" bitdiffs="cc == 11 && size == 01">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="halfprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELGT" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELGT-halfprec" />
|
|
</docvars>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
|
|
</arch_variants>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELGT.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VSELGT_T1_S" oneofinclass="12" oneof="24" label="Greater than, single-precision scalar" bitdiffs="cc == 11 && size == 10">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="singleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELGT" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELGT-singleprec" />
|
|
</docvars>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELGT.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VSELGT_T1_D" oneofinclass="12" oneof="24" label="Greater than, double-precision scalar" bitdiffs="cc == 11 && size == 11">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="doubleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELGT" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELGT-doubleprec" />
|
|
</docvars>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELGT.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VSELVS_T1_H" oneofinclass="12" oneof="24" label="Unordered, half-precision scalar" bitdiffs="cc == 01 && size == 01">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="halfprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELVS" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELVS-halfprec" />
|
|
</docvars>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
|
|
</arch_variants>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELVS.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VSELVS_T1_S" oneofinclass="12" oneof="24" label="Unordered, single-precision scalar" bitdiffs="cc == 01 && size == 10">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="singleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELVS" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELVS-singleprec" />
|
|
</docvars>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELVS.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VSELVS_T1_D" oneofinclass="12" oneof="24" label="Unordered, double-precision scalar" bitdiffs="cc == 01 && size == 11">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="doubleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VSELVS" />
|
|
<docvar key="mnemonic-fpdatasize" value="VSELVS-doubleprec" />
|
|
</docvars>
|
|
<box hibit="21" width="2" name="cc">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate comment="Not permitted in IT block"><text>VSELVS.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VSEL/T1_A.txt" mylink="aarch32.instrs.VSEL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
|
|
if size == '00' || (size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
|
|
integer esize;
|
|
integer d;
|
|
integer n;
|
|
integer m;
|
|
case size of
|
|
when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
|
|
when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
|
|
when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
|
|
cond = cc:(cc<1> EOR cc<0>):'0';</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<constrained_unpredictables encoding="T1" ps_block="Decode">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">InITBlock()</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
|
|
</cu_type>
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
|
|
</cu_type>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="VSELEQ_A1_D, VSELEQ_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dd"><Dd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VSELEQ_A1_D, VSELEQ_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dn"><Dn></symbol>
|
|
<account encodedin="N:Vn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VSELEQ_A1_D, VSELEQ_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dm"><Dm></symbol>
|
|
<account encodedin="M:Vm">
|
|
<intro>
|
|
<para>Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VSELEQ_A1_H, VSELEQ_T1_H" symboldefcount="1">
|
|
<symbol link="sa_sd"><Sd></symbol>
|
|
<account encodedin="Vd:D">
|
|
<intro>
|
|
<para>Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VSELEQ_A1_H, VSELEQ_T1_H" symboldefcount="1">
|
|
<symbol link="sa_sn"><Sn></symbol>
|
|
<account encodedin="Vn:N">
|
|
<intro>
|
|
<para>Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VSELEQ_A1_H, VSELEQ_T1_H" symboldefcount="1">
|
|
<symbol link="sa_sm"><Sm></symbol>
|
|
<account encodedin="Vm:M">
|
|
<intro>
|
|
<para>Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VSEL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);
|
|
case esize of
|
|
when 16
|
|
<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : (if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(cond) then <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n] else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m])<15:0>;
|
|
when 32
|
|
<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(cond) then <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n] else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m];
|
|
when 64
|
|
<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(cond) then <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n] else <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m];</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|