296 lines
16 KiB
XML
296 lines
16 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VRSHR_VORR_r" title="VRSHR (zero) -- AArch32" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="VRSHR" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VORR" />
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</docvars>
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<heading>VRSHR (zero)</heading>
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<desc>
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<brief>Vector Rounding Shift Right</brief>
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<longer> copies the contents of one SIMD register to another</longer>
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</desc>
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<aliasto refiform="vorr_r.xml" iformid="VORR_r">VORR (register)</aliasto>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VORR" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="size" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="opc" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="o1" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VRSHR_VORR_r_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="alias_mnemonic" value="VRSHR" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VORR" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64"><dt></a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&FP source register (field "N:Vn")"><Dm></a><text>, #0</text></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="vorr_r.xml#VORR_r_A1_D">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64"><dt></a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&FP source register (field "N:Vn")"><Dm></a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&FP source register (field "N:Vn")"><Dm></a></asmtemplate>
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<aliascond>Never</aliascond>
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</equivalent_to>
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</encoding>
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<encoding name="VRSHR_VORR_r_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="alias_mnemonic" value="VRSHR" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VORR" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64"><dt></a><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&FP source register (field "N:Vn")"><Qm></a><text>, #0</text></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="vorr_r.xml#VORR_r_A1_Q">VORR</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64"><dt></a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&FP source register (field "N:Vn")"><Qm></a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&FP source register (field "N:Vn")"><Qm></a></asmtemplate>
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<aliascond>Never</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VORR" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="">
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<box hibit="31" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="28" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="size" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="opc" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="o1" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VRSHR_VORR_r_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="alias_mnemonic" value="VRSHR" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VORR" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64"><dt></a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&FP source register (field "N:Vn")"><Dm></a><text>, #0</text></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="vorr_r.xml#VORR_r_T1_D">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64"><dt></a><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&FP source register (field "N:Vn")"><Dm></a><text>, </text><a link="sa_dm_1" hover="64-bit SIMD&FP source register (field "N:Vn")"><Dm></a></asmtemplate>
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<aliascond>Never</aliascond>
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</equivalent_to>
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</encoding>
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<encoding name="VRSHR_VORR_r_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="alias_mnemonic" value="VRSHR" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VORR" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VRSHR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64"><dt></a><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&FP source register (field "N:Vn")"><Qm></a><text>, #0</text></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="vorr_r.xml#VORR_r_T1_Q">VORR</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_dt_2" hover="Data type for elements of vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64"><dt></a><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&FP source register (field "N:Vn")"><Qm></a><text>, </text><a link="sa_qm_1" hover="128-bit SIMD&FP source register (field "N:Vn")"><Qm></a></asmtemplate>
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<aliascond>Never</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VRSHR_VORR_r_A1_Q" symboldefcount="1">
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<symbol link="sa_c_1"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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</docvars>
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<intro>
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<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VRSHR_VORR_r_T1_Q" symboldefcount="2">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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</docvars>
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<intro>
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<para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VRSHR_VORR_r_A1_Q, VRSHR_VORR_r_T1_Q" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VRSHR_VORR_r_A1_Q, VRSHR_VORR_r_T1_Q" symboldefcount="1">
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<symbol link="sa_dt_2"><dt></symbol>
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<account encodedin="">
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<intro>
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<para>Is the data type for the elements of the vectors, and must be one of: S8, S16, S32, S64, U8, U16, U32 or U64.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VRSHR_VORR_r_A1_Q, VRSHR_VORR_r_T1_Q" symboldefcount="1">
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<symbol link="sa_qd"><Qd></symbol>
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<account encodedin="D:Vd">
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<intro>
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<para>Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VRSHR_VORR_r_A1_Q, VRSHR_VORR_r_T1_Q" symboldefcount="1">
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<symbol link="sa_qm_1"><Qm></symbol>
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<account encodedin="N:Vn" and "M:Vm">
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<intro>
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<para>Is the 128-bit name of the SIMD&FP source register, encoded in the "N:Vn" and "M:Vm" field as <Qm>*2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VRSHR_VORR_r_A1_D, VRSHR_VORR_r_T1_D" symboldefcount="1">
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<symbol link="sa_dd"><Dd></symbol>
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<account encodedin="D:Vd">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VRSHR_VORR_r_A1_D, VRSHR_VORR_r_T1_D" symboldefcount="1">
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<symbol link="sa_dm_1"><Dm></symbol>
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<account encodedin="N:Vn" and "M:Vm">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP source register, encoded in the "N:Vn" and "M:Vm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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</instructionsection>
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