363 lines
20 KiB
XML
363 lines
20 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VRINTX_vfp" title="VRINTX (floating-point) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VRINTX" />
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</docvars>
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<heading>VRINTX (floating-point)</heading>
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<desc>
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<brief>
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<para>Round floating-point to integer inexact</para>
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</brief>
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<authored>
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<para>Round floating-point to integer inexact rounds a floating-point value to an integral floating-point value of the same size, using the rounding mode specified in the FPSCR, and raises an Inexact exception when the result value is not numerically equal to the input value. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VRINTX" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VRINTX_vfp/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="19" name="o1" settings="1">
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<c>0</c>
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</box>
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<box hibit="18" width="3" name="opc2" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="7" name="o3" settings="1">
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<c>0</c>
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</box>
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<box hibit="6" settings="1">
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<c>1</c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VRINTX_vfp_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="halfprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VRINTX" />
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<docvar key="mnemonic-fpdatasize" value="VRINTX-halfprec" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="9" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sm" hover="32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VRINTX_vfp_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VRINTX" />
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<docvar key="mnemonic-fpdatasize" value="VRINTX-singleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sm" hover="32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VRINTX_vfp_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VRINTX" />
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<docvar key="mnemonic-fpdatasize" value="VRINTX-doubleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dm" hover="64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VRINTX_vfp/A1_A.txt" mylink="aarch32.instrs.VRINTX_vfp.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '00' || (size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
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if size == '01' && cond != '1110' then UNPREDICTABLE;
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exact = TRUE;
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integer esize;
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integer d;
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integer m;
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case size of
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when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
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when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
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when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VRINTX" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VRINTX_vfp/T1_A.txt">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="19" name="o1" settings="1">
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<c>0</c>
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</box>
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<box hibit="18" width="3" name="opc2" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="7" name="o3" settings="1">
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<c>0</c>
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</box>
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<box hibit="6" settings="1">
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<c>1</c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VRINTX_vfp_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="fpdatasize" value="halfprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VRINTX" />
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<docvar key="mnemonic-fpdatasize" value="VRINTX-halfprec" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="9" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sm" hover="32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VRINTX_vfp_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VRINTX" />
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<docvar key="mnemonic-fpdatasize" value="VRINTX-singleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sm" hover="32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VRINTX_vfp_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VRINTX" />
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<docvar key="mnemonic-fpdatasize" value="VRINTX-doubleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VRINTX</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dm" hover="64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VRINTX_vfp/T1_A.txt" mylink="aarch32.instrs.VRINTX_vfp.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '00' || (size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
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if size == '01' && <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
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exact = TRUE;
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integer esize;
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integer d;
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integer m;
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case size of
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when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
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when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
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when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="T1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">InITBlock()</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type>
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<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
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</cu_type>
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<cu_type>
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<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
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</cu_type>
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<arch_variants>
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<arch_variant name="ARMv8.2-A" />
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</arch_variants>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VRINTX_vfp_A1_H, VRINTX_vfp_T1_H" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VRINTX_vfp_A1_H, VRINTX_vfp_T1_H" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VRINTX_vfp_A1_H, VRINTX_vfp_T1_H" symboldefcount="1">
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<symbol link="sa_sd"><Sd></symbol>
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<account encodedin="Vd:D">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VRINTX_vfp_A1_H, VRINTX_vfp_T1_H" symboldefcount="1">
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<symbol link="sa_sm"><Sm></symbol>
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<account encodedin="Vm:M">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VRINTX_vfp_A1_D, VRINTX_vfp_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dd"><Dd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VRINTX_vfp_A1_D, VRINTX_vfp_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dm"><Dm></symbol>
|
|
<account encodedin="M:Vm">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VRINTX_vfp/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);
|
|
rounding = <a link="impl-shared.FPRoundingMode.1" file="shared_pseudocode.xml" hover="function: FPRounding FPRoundingMode(FPCRType fpcr)">FPRoundingMode</a>(FPSCR[]);
|
|
case esize of
|
|
when 16
|
|
<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]<15:0>, FPSCR[], rounding, exact);
|
|
when 32
|
|
<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], rounding, exact);
|
|
when 64
|
|
<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPRoundInt.4" file="shared_pseudocode.xml" hover="function: bits(N) FPRoundInt(bits(N) op, FPCRType fpcr, FPRounding rounding, boolean exact)">FPRoundInt</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], rounding, exact);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|