381 lines
20 KiB
XML
381 lines
20 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="VQSUB" title="VQSUB -- AArch32" type="instruction">
|
|
<docvars>
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="mnemonic" value="VQSUB" />
|
|
</docvars>
|
|
<heading>VQSUB</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Vector Saturating Subtract</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Vector Saturating Subtract subtracts the elements of the second operand vector from the corresponding elements of the first operand vector, and places the results in the destination vector. Signed and unsigned operations are distinct.</para>
|
|
<para>The operand and result elements must all be the same type, and can be any one of:</para>
|
|
<list type="unordered">
|
|
<listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
|
|
<listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
|
|
</list>
|
|
<para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
|
|
<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
|
|
</authored>
|
|
</desc>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<classesintro count="2">
|
|
<txt>It has encodings from the following instruction sets:</txt>
|
|
<txt> A32 (</txt>
|
|
<a href="#iclass_a1">A1</a>
|
|
<txt>)</txt>
|
|
<txt> and </txt>
|
|
<txt> T32 (</txt>
|
|
<a href="#iclass_t1">T1</a>
|
|
<txt>)</txt>
|
|
<txt>.</txt>
|
|
</classesintro>
|
|
<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VQSUB" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="32" psname="aarch32/instrs/VQSUB/T1A1_A.txt">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="24" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Vn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="opc" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="6" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" name="o1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Vm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VQSUB_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VQSUB" />
|
|
<docvar key="simdvectorsize" value="double" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VQSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field "U:size") [S8,S16,S32,S64,U8,U16,U32,U64]"><dt></a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VQSUB_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VQSUB" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VQSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field "U:size") [S8,S16,S32,S64,U8,U16,U32,U64]"><dt></a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&FP source register (field "N:Vn")"><Qn></a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&FP source register (field "M:Vm")"><Qm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VQSUB/T1A1_A.txt" mylink="aarch32.instrs.VQSUB.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
|
|
unsigned = (U == '1');
|
|
esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size); elements = 64 DIV esize;
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VQSUB" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VQSUB/T1A1_A.txt">
|
|
<box hibit="31" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="28" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="27" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Vn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="opc" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="6" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" name="o1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Vm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VQSUB_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VQSUB" />
|
|
<docvar key="simdvectorsize" value="double" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VQSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field "U:size") [S8,S16,S32,S64,U8,U16,U32,U64]"><dt></a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>,</text><text>}</text><text> </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VQSUB_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VQSUB" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VQSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field "U:size") [S8,S16,S32,S64,U8,U16,U32,U64]"><dt></a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>,</text><text>}</text><text> </text><a link="sa_qn" hover="First 128-bit SIMD&FP source register (field "N:Vn")"><Qn></a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&FP source register (field "M:Vm")"><Qm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VQSUB/T1A1_A.txt" mylink="aarch32.instrs.VQSUB.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
|
|
unsigned = (U == '1');
|
|
esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size); elements = 64 DIV esize;
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="VQSUB_A1_Q" symboldefcount="1">
|
|
<symbol link="sa_c_1"><c></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VQSUB_T1_Q" symboldefcount="2">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VQSUB_A1_Q, VQSUB_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VQSUB_A1_Q, VQSUB_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_dt"><dt></symbol>
|
|
<definition encodedin="U:size">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">U</entry>
|
|
<entry class="bitfield">size</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">S8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">S64</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">U8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">U64</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="VQSUB_A1_Q, VQSUB_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_qd"><Qd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VQSUB_A1_Q, VQSUB_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_qn"><Qn></symbol>
|
|
<account encodedin="N:Vn">
|
|
<intro>
|
|
<para>Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VQSUB_A1_Q, VQSUB_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_qm"><Qm></symbol>
|
|
<account encodedin="M:Vm">
|
|
<intro>
|
|
<para>Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VQSUB_A1_D, VQSUB_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dd"><Dd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VQSUB_A1_D, VQSUB_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dn"><Dn></symbol>
|
|
<account encodedin="N:Vn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VQSUB_A1_D, VQSUB_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dm"><Dm></symbol>
|
|
<account encodedin="M:Vm">
|
|
<intro>
|
|
<para>Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VQSUB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
|
|
for r = 0 to regs-1
|
|
for e = 0 to elements-1
|
|
diff = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], unsigned) - <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned);
|
|
boolean sat;
|
|
(<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize], sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(diff, esize, unsigned);
|
|
if sat then FPSCR.QC = '1';</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|