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slonik/specs/vqshrun_vqmovn.xml

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="VQSHRUN_VQMOVN" title="VQSHRUN (zero) -- AArch32" type="alias">
<docvars>
<docvar key="alias_mnemonic" value="VQSHRUN" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="mnemonic" value="VQMOVUN" />
<docvar key="result-type" value="unsigned-result" />
</docvars>
<heading>VQSHRUN (zero)</heading>
<desc>
<brief>Vector Saturating Shift Right, Narrow</brief>
<longer> takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the unsigned truncated results in a doubleword vector</longer>
</desc>
<aliasto refiform="vqmovn.xml" iformid="VQMOVN">VQMOVN, VQMOVUN</aliasto>
<classes>
<classesintro count="2">
<txt>It has encodings from the following instruction sets:</txt>
<txt> A32 (</txt>
<a href="#iclass_a1">A1</a>
<txt>)</txt>
<txt> and </txt>
<txt> T32 (</txt>
<a href="#iclass_t1">T1</a>
<txt>)</txt>
<txt>.</txt>
</classesintro>
<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
<docvars>
<docvar key="armarmheading" value="A1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="A32" />
</docvars>
<iclassintro count="1"></iclassintro>
<regdiagram form="32" psname="" tworows="1">
<box hibit="31" width="9" settings="9">
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>1</c>
<c>1</c>
<c>1</c>
</box>
<box hibit="22" name="D" usename="1">
<c></c>
</box>
<box hibit="21" width="2" settings="2">
<c>1</c>
<c>1</c>
</box>
<box hibit="19" width="2" name="size" usename="1">
<c colspan="2"></c>
</box>
<box hibit="17" width="2" name="opc1" settings="2">
<c>1</c>
<c>0</c>
</box>
<box hibit="15" width="4" name="Vd" usename="1">
<c colspan="4"></c>
</box>
<box hibit="11" settings="1">
<c>0</c>
</box>
<box hibit="10" width="3" settings="3">
<c>0</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="7" width="2" name="op" usename="1" settings="2">
<c>0</c>
<c>1</c>
</box>
<box hibit="5" name="M" usename="1">
<c></c>
</box>
<box hibit="4" settings="1">
<c>0</c>
</box>
<box hibit="3" width="4" name="Vm" usename="1">
<c colspan="4"></c>
</box>
</regdiagram>
<encoding name="VQSHRUN_VQMOVUN_A1" oneofinclass="1" oneof="2" label="Unsigned result">
<docvars>
<docvar key="alias_mnemonic" value="VQSHRUN" />
<docvar key="armarmheading" value="A1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="A32" />
<docvar key="mnemonic" value="VQMOVUN" />
<docvar key="result-type" value="unsigned-result" />
</docvars>
<asmtemplate><text>VQSHRUN</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
<equivalent_to>
<asmtemplate><a href="vqmovn.xml#VQMOVUN_A1">VQMOVUN</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
<aliascond>Never</aliascond>
</equivalent_to>
</encoding>
</iclass>
<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
<docvars>
<docvar key="armarmheading" value="T1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="T32" />
</docvars>
<iclassintro count="1"></iclassintro>
<regdiagram form="16x2" psname="" tworows="1">
<box hibit="31" width="9" settings="9">
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
</box>
<box hibit="22" name="D" usename="1">
<c></c>
</box>
<box hibit="21" width="2" settings="2">
<c>1</c>
<c>1</c>
</box>
<box hibit="19" width="2" name="size" usename="1">
<c colspan="2"></c>
</box>
<box hibit="17" width="2" name="opc1" settings="2">
<c>1</c>
<c>0</c>
</box>
<box hibit="15" width="4" name="Vd" usename="1">
<c colspan="4"></c>
</box>
<box hibit="11" settings="1">
<c>0</c>
</box>
<box hibit="10" width="3" settings="3">
<c>0</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="7" width="2" name="op" usename="1" settings="2">
<c>0</c>
<c>1</c>
</box>
<box hibit="5" name="M" usename="1">
<c></c>
</box>
<box hibit="4" settings="1">
<c>0</c>
</box>
<box hibit="3" width="4" name="Vm" usename="1">
<c colspan="4"></c>
</box>
</regdiagram>
<encoding name="VQSHRUN_VQMOVUN_T1" oneofinclass="1" oneof="2" label="Unsigned result">
<docvars>
<docvar key="alias_mnemonic" value="VQSHRUN" />
<docvar key="armarmheading" value="T1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="T32" />
<docvar key="mnemonic" value="VQMOVUN" />
<docvar key="result-type" value="unsigned-result" />
</docvars>
<asmtemplate><text>VQSHRUN</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, #0</text></asmtemplate>
<equivalent_to>
<asmtemplate><a href="vqmovn.xml#VQMOVUN_T1">VQMOVUN</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt_1" hover="Data type for elements of operand (field &quot;size&quot;) [S16,S32,S64,UNDEFINED]">&lt;dt&gt;</a><text> </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_qm" hover="128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
<aliascond>Never</aliascond>
</equivalent_to>
</encoding>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="VQSHRUN_VQMOVUN_A1" symboldefcount="1">
<symbol link="sa_c_1">&lt;c&gt;</symbol>
<account encodedin="">
<docvars>
<docvar key="armarmheading" value="A1" />
</docvars>
<intro>
<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQSHRUN_VQMOVUN_T1" symboldefcount="2">
<symbol link="sa_c">&lt;c&gt;</symbol>
<account encodedin="">
<docvars>
<docvar key="armarmheading" value="T1" />
</docvars>
<intro>
<para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQSHRUN_VQMOVUN_A1, VQSHRUN_VQMOVUN_T1" symboldefcount="1">
<symbol link="sa_q">&lt;q&gt;</symbol>
<account encodedin="">
<intro>
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQSHRUN_VQMOVUN_A1, VQSHRUN_VQMOVUN_T1" symboldefcount="1">
<symbol link="sa_dt_1">&lt;dt&gt;</symbol>
<definition encodedin="size">
<intro>Is the data type for the elements of the operand, </intro>
<table class="valuetable">
<tgroup cols="2">
<thead>
<row>
<entry class="bitfield">size</entry>
<entry class="symbol">&lt;dt&gt;</entry>
</row>
</thead>
<tbody>
<row>
<entry class="bitfield">00</entry>
<entry class="symbol">S16</entry>
</row>
<row>
<entry class="bitfield">01</entry>
<entry class="symbol">S32</entry>
</row>
<row>
<entry class="bitfield">10</entry>
<entry class="symbol">S64</entry>
</row>
<row>
<entry class="bitfield">11</entry>
<entry class="symbol">RESERVED</entry>
</row>
</tbody>
</tgroup>
</table>
</definition>
</explanation>
<explanation enclist="VQSHRUN_VQMOVUN_A1, VQSHRUN_VQMOVUN_T1" symboldefcount="1">
<symbol link="sa_dd">&lt;Dd&gt;</symbol>
<account encodedin="D:Vd">
<intro>
<para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQSHRUN_VQMOVUN_A1, VQSHRUN_VQMOVUN_T1" symboldefcount="1">
<symbol link="sa_qm">&lt;Qm&gt;</symbol>
<account encodedin="M:Vm">
<intro>
<para>Is the 128-bit name of the SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
</intro>
</account>
</explanation>
</explanations>
</instructionsection>
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