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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="VQRSHL" title="VQRSHL -- AArch32" type="instruction">
<docvars>
<docvar key="instr-class" value="fpsimd" />
<docvar key="mnemonic" value="VQRSHL" />
</docvars>
<heading>VQRSHL</heading>
<desc>
<brief>
<para>Vector Saturating Rounding Shift Left</para>
</brief>
<authored>
<para>Vector Saturating Rounding Shift Left takes each element in a vector, shifts them by a value from the least significant byte of the corresponding element of a second vector, and places the results in the destination vector. If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift.</para>
<para>For truncated results see <xref linkend="A32T32-fpsimd.instructions.VQSHL_r">VQSHL (register)</xref>.</para>
<para>The first operand and result elements are the same data type, and can be any one of:</para>
<list type="unordered">
<listitem><content>8-bit, 16-bit, 32-bit, or 64-bit signed integers.</content></listitem>
<listitem><content>8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.</content></listitem>
</list>
<para>The second operand is a signed integer of the same size.</para>
<para>If any of the results overflow, they are saturated. The cumulative saturation bit, <xref linkend="AArch32.fpscr">FPSCR</xref>.QC, is set if saturation occurs. For details see <xref linkend="BEIHABGJ">Pseudocode details of saturation</xref>.</para>
<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
</authored>
</desc>
<alias_list howmany="0"></alias_list>
<classes>
<classesintro count="2">
<txt>It has encodings from the following instruction sets:</txt>
<txt> A32 (</txt>
<a href="#iclass_a1">A1</a>
<txt>)</txt>
<txt> and </txt>
<txt> T32 (</txt>
<a href="#iclass_t1">T1</a>
<txt>)</txt>
<txt>.</txt>
</classesintro>
<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
<docvars>
<docvar key="armarmheading" value="A1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="A32" />
<docvar key="mnemonic" value="VQRSHL" />
</docvars>
<iclassintro count="2"></iclassintro>
<regdiagram form="32" psname="aarch32/instrs/VQRSHL/T1A1_A.txt">
<box hibit="31" width="7" settings="7">
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>0</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="24" name="U" usename="1">
<c></c>
</box>
<box hibit="23" settings="1">
<c>0</c>
</box>
<box hibit="22" name="D" usename="1">
<c></c>
</box>
<box hibit="21" width="2" name="size" usename="1">
<c colspan="2"></c>
</box>
<box hibit="19" width="4" name="Vn" usename="1">
<c colspan="4"></c>
</box>
<box hibit="15" width="4" name="Vd" usename="1">
<c colspan="4"></c>
</box>
<box hibit="11" width="4" name="opc" settings="4">
<c>0</c>
<c>1</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="7" name="N" usename="1">
<c></c>
</box>
<box hibit="6" name="Q" usename="1">
<c></c>
</box>
<box hibit="5" name="M" usename="1">
<c></c>
</box>
<box hibit="4" name="o1" settings="1">
<c>1</c>
</box>
<box hibit="3" width="4" name="Vm" usename="1">
<c colspan="4"></c>
</box>
</regdiagram>
<encoding name="VQRSHL_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
<docvars>
<docvar key="armarmheading" value="A1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="A32" />
<docvar key="mnemonic" value="VQRSHL" />
<docvar key="simdvectorsize" value="double" />
</docvars>
<box hibit="6" width="1" name="Q">
<c>0</c>
</box>
<asmtemplate><text>VQRSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
</encoding>
<encoding name="VQRSHL_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
<docvars>
<docvar key="armarmheading" value="A1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="A32" />
<docvar key="mnemonic" value="VQRSHL" />
<docvar key="simdvectorsize" value="quad" />
</docvars>
<box hibit="6" width="1" name="Q">
<c>1</c>
</box>
<asmtemplate><text>VQRSHL</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="aarch32/instrs/VQRSHL/T1A1_A.txt" mylink="aarch32.instrs.VQRSHL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;
unsigned = (U == '1');
esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size); elements = 64 DIV esize;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); regs = if Q == '0' then 1 else 2;</pstext>
</ps>
</ps_section>
</iclass>
<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
<docvars>
<docvar key="armarmheading" value="T1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="T32" />
<docvar key="mnemonic" value="VQRSHL" />
</docvars>
<iclassintro count="2"></iclassintro>
<regdiagram form="16x2" psname="aarch32/instrs/VQRSHL/T1A1_A.txt">
<box hibit="31" width="3" settings="3">
<c>1</c>
<c>1</c>
<c>1</c>
</box>
<box hibit="28" name="U" usename="1">
<c></c>
</box>
<box hibit="27" width="5" settings="5">
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="22" name="D" usename="1">
<c></c>
</box>
<box hibit="21" width="2" name="size" usename="1">
<c colspan="2"></c>
</box>
<box hibit="19" width="4" name="Vn" usename="1">
<c colspan="4"></c>
</box>
<box hibit="15" width="4" name="Vd" usename="1">
<c colspan="4"></c>
</box>
<box hibit="11" width="4" name="opc" settings="4">
<c>0</c>
<c>1</c>
<c>0</c>
<c>1</c>
</box>
<box hibit="7" name="N" usename="1">
<c></c>
</box>
<box hibit="6" name="Q" usename="1">
<c></c>
</box>
<box hibit="5" name="M" usename="1">
<c></c>
</box>
<box hibit="4" name="o1" settings="1">
<c>1</c>
</box>
<box hibit="3" width="4" name="Vm" usename="1">
<c colspan="4"></c>
</box>
</regdiagram>
<encoding name="VQRSHL_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
<docvars>
<docvar key="armarmheading" value="T1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="T32" />
<docvar key="mnemonic" value="VQRSHL" />
<docvar key="simdvectorsize" value="double" />
</docvars>
<box hibit="6" width="1" name="Q">
<c>0</c>
</box>
<asmtemplate><text>VQRSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a></asmtemplate>
</encoding>
<encoding name="VQRSHL_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
<docvars>
<docvar key="armarmheading" value="T1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="T32" />
<docvar key="mnemonic" value="VQRSHL" />
<docvar key="simdvectorsize" value="quad" />
</docvars>
<box hibit="6" width="1" name="Q">
<c>1</c>
</box>
<asmtemplate><text>VQRSHL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;c&gt;</a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field &quot;U:size&quot;) [S8,S16,S32,S64,U8,U16,U32,U64]">&lt;dt&gt;</a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>,</text><text>}</text><text> </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="aarch32/instrs/VQRSHL/T1A1_A.txt" mylink="aarch32.instrs.VQRSHL.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' || Vn&lt;0&gt; == '1') then UNDEFINED;
unsigned = (U == '1');
esize = 8 &lt;&lt; <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size); elements = 64 DIV esize;
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); regs = if Q == '0' then 1 else 2;</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="VQRSHL_A1_Q" symboldefcount="1">
<symbol link="sa_c_1">&lt;c&gt;</symbol>
<account encodedin="">
<docvars>
<docvar key="armarmheading" value="A1" />
<docvar key="isa" value="A32" />
</docvars>
<intro>
<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQRSHL_T1_Q" symboldefcount="2">
<symbol link="sa_c">&lt;c&gt;</symbol>
<account encodedin="">
<docvars>
<docvar key="armarmheading" value="T1" />
<docvar key="isa" value="T32" />
</docvars>
<intro>
<para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQRSHL_A1_Q, VQRSHL_T1_Q" symboldefcount="1">
<symbol link="sa_q">&lt;q&gt;</symbol>
<account encodedin="">
<intro>
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQRSHL_A1_Q, VQRSHL_T1_Q" symboldefcount="1">
<symbol link="sa_dt">&lt;dt&gt;</symbol>
<definition encodedin="U:size">
<intro>Is the data type for the elements of the vectors, </intro>
<table class="valuetable">
<tgroup cols="3">
<thead>
<row>
<entry class="bitfield">U</entry>
<entry class="bitfield">size</entry>
<entry class="symbol">&lt;dt&gt;</entry>
</row>
</thead>
<tbody>
<row>
<entry class="bitfield">0</entry>
<entry class="bitfield">00</entry>
<entry class="symbol">S8</entry>
</row>
<row>
<entry class="bitfield">0</entry>
<entry class="bitfield">01</entry>
<entry class="symbol">S16</entry>
</row>
<row>
<entry class="bitfield">0</entry>
<entry class="bitfield">10</entry>
<entry class="symbol">S32</entry>
</row>
<row>
<entry class="bitfield">0</entry>
<entry class="bitfield">11</entry>
<entry class="symbol">S64</entry>
</row>
<row>
<entry class="bitfield">1</entry>
<entry class="bitfield">00</entry>
<entry class="symbol">U8</entry>
</row>
<row>
<entry class="bitfield">1</entry>
<entry class="bitfield">01</entry>
<entry class="symbol">U16</entry>
</row>
<row>
<entry class="bitfield">1</entry>
<entry class="bitfield">10</entry>
<entry class="symbol">U32</entry>
</row>
<row>
<entry class="bitfield">1</entry>
<entry class="bitfield">11</entry>
<entry class="symbol">U64</entry>
</row>
</tbody>
</tgroup>
</table>
</definition>
</explanation>
<explanation enclist="VQRSHL_A1_Q, VQRSHL_T1_Q" symboldefcount="1">
<symbol link="sa_qd">&lt;Qd&gt;</symbol>
<account encodedin="D:Vd">
<intro>
<para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQRSHL_A1_Q, VQRSHL_T1_Q" symboldefcount="1">
<symbol link="sa_qm">&lt;Qm&gt;</symbol>
<account encodedin="M:Vm">
<intro>
<para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQRSHL_A1_Q, VQRSHL_T1_Q" symboldefcount="1">
<symbol link="sa_qn">&lt;Qn&gt;</symbol>
<account encodedin="N:Vn">
<intro>
<para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQRSHL_A1_D, VQRSHL_T1_D" symboldefcount="1">
<symbol link="sa_dd">&lt;Dd&gt;</symbol>
<account encodedin="D:Vd">
<intro>
<para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQRSHL_A1_D, VQRSHL_T1_D" symboldefcount="1">
<symbol link="sa_dm">&lt;Dm&gt;</symbol>
<account encodedin="M:Vm">
<intro>
<para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="VQRSHL_A1_D, VQRSHL_T1_D" symboldefcount="1">
<symbol link="sa_dn">&lt;Dn&gt;</symbol>
<account encodedin="N:Vn">
<intro>
<para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="aarch32/instrs/VQRSHL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
bits(esize) result;
boolean sat;
for r = 0 to regs-1
for e = 0 to elements-1
integer element = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r], e, esize], unsigned);
integer shift = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r], e, esize]&lt;7:0&gt;);
if shift &gt;= 0 then // left shift
element = element &lt;&lt; shift;
else // rounding right shift
shift = -shift;
element = (element + (1 &lt;&lt; (shift - 1))) &gt;&gt; shift;
(result, sat) = <a link="impl-shared.SatQ.3" file="shared_pseudocode.xml" hover="function: (bits(N), boolean) SatQ(integer i, integer N, boolean unsigned)">SatQ</a>(element, esize, unsigned);
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r], e, esize] = result;
if sat then FPSCR.QC = '1';</pstext>
</ps>
</ps_section>
</instructionsection>
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