378 lines
18 KiB
XML
378 lines
18 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VPOP_VLDM" title="VPOP -- AArch32" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="VPOP" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="ldmstm-mode" value="inc-after" />
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<docvar key="mnemonic" value="VLDM" />
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</docvars>
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<heading>VPOP</heading>
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<desc>
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<brief>
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<para>Pop SIMD&FP registers from stack</para>
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</brief>
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<authored>
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<para>Pop SIMD&FP registers from stack loads multiple consecutive Advanced SIMD and floating-point register file registers from the stack.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<aliasto refiform="vldm.xml" iformid="VLDM">VLDM, VLDMDB, VLDMIA</aliasto>
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<classes>
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<classesintro count="4">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt> and </txt>
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<a href="#iclass_a2">A2</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t2">T2</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" name="U" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="W" usename="1" settings="1" psbits="1">
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<c>1</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="7" width="7" name="imm8<7:1>" usename="1">
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<c colspan="7"></c>
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</box>
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<box hibit="0" name="imm8<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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</regdiagram>
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<encoding name="VPOP_VLDM_A1" oneofinclass="1" oneof="4" label="Increment After">
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<docvars>
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<docvar key="alias_mnemonic" value="VPOP" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="ldmstm-mode" value="inc-after" />
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<docvar key="mnemonic" value="VLDM" />
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<docvar key="mnemonic-fpdatasize" value="VLDM-doubleprec" />
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</docvars>
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<asmtemplate><text>VPOP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&FP registers to be transferred (field "D:Vd")"><dreglist></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="vldm.xml#VLDM_A1">VLDM</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> SP!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&FP registers to be transferred (field "D:Vd")"><dreglist></a></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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<iclass name="A2" oneof="4" id="iclass_a2" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" name="U" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="W" usename="1" settings="1" psbits="1">
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<c>1</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="VPOP_VLDM_A2" oneofinclass="1" oneof="4" label="Increment After">
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<docvars>
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<docvar key="alias_mnemonic" value="VPOP" />
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<docvar key="armarmheading" value="A2" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="ldmstm-mode" value="inc-after" />
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<docvar key="mnemonic" value="VLDM" />
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<docvar key="mnemonic-fpdatasize" value="VLDM-singleprec" />
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</docvars>
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<asmtemplate><text>VPOP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&FP registers to be transferred (field "Vd:D")"><sreglist></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="vldm.xml#VLDM_A2">VLDM</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> SP!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&FP registers to be transferred (field "Vd:D")"><sreglist></a></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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<iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" name="U" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="W" usename="1" settings="1" psbits="1">
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<c>1</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="7" width="7" name="imm8<7:1>" usename="1">
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<c colspan="7"></c>
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</box>
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<box hibit="0" name="imm8<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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</regdiagram>
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<encoding name="VPOP_VLDM_T1" oneofinclass="1" oneof="4" label="Increment After">
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<docvars>
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<docvar key="alias_mnemonic" value="VPOP" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="ldmstm-mode" value="inc-after" />
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<docvar key="mnemonic" value="VLDM" />
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<docvar key="mnemonic-fpdatasize" value="VLDM-doubleprec" />
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</docvars>
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<asmtemplate><text>VPOP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&FP registers to be transferred (field "D:Vd")"><dreglist></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="vldm.xml#VLDM_T1">VLDM</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> SP!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&FP registers to be transferred (field "D:Vd")"><dreglist></a></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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<iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" name="U" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="W" usename="1" settings="1" psbits="1">
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<c>1</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="VPOP_VLDM_T2" oneofinclass="1" oneof="4" label="Increment After">
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<docvars>
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<docvar key="alias_mnemonic" value="VPOP" />
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<docvar key="armarmheading" value="T2" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="ldmstm-mode" value="inc-after" />
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<docvar key="mnemonic" value="VLDM" />
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<docvar key="mnemonic-fpdatasize" value="VLDM-singleprec" />
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</docvars>
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<asmtemplate><text>VPOP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&FP registers to be transferred (field "Vd:D")"><sreglist></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="vldm.xml#VLDM_T2">VLDM</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> SP!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&FP registers to be transferred (field "Vd:D")"><sreglist></a></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VPOP_VLDM_A1, VPOP_VLDM_A2, VPOP_VLDM_T1, VPOP_VLDM_T2" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VPOP_VLDM_A1, VPOP_VLDM_A2, VPOP_VLDM_T1, VPOP_VLDM_T2" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VPOP_VLDM_A1, VPOP_VLDM_A2, VPOP_VLDM_T1, VPOP_VLDM_T2" symboldefcount="1">
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<symbol link="sa_size"><size></symbol>
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<account encodedin="">
|
|
<intro>
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<para>An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred.</para>
|
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</intro>
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|
</account>
|
|
</explanation>
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|
<explanation enclist="VPOP_VLDM_A2, VPOP_VLDM_T2" symboldefcount="1">
|
|
<symbol link="sa_sreglist"><sreglist></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Is the list of consecutively numbered 32-bit SIMD&FP registers to be transferred. The first register in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must contain at least one register.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VPOP_VLDM_A1, VPOP_VLDM_T1" symboldefcount="1">
|
|
<symbol link="sa_dreglist"><dreglist></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Is the list of consecutively numbered 64-bit SIMD&FP registers to be transferred. The first register in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The list must contain at least one register, and must not contain more than 16 registers.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
</instructionsection>
|