343 lines
18 KiB
XML
343 lines
18 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VMRS" title="VMRS -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VMRS" />
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</docvars>
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<heading>VMRS</heading>
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<desc>
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<brief>
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<para>Move SIMD&FP Special register to general-purpose register</para>
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</brief>
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<authored>
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<para>Move SIMD&FP Special register to general-purpose register moves the value of an Advanced SIMD and floating-point System register to a general-purpose register. When the specified System register is the <xref linkend="AArch32.fpscr">FPSCR</xref>, a form of the instruction transfers the <xref linkend="AArch32.fpscr">FPSCR</xref>.{N, Z, C, V} condition flags to the <xref linkend="AArch32.apsr">APSR</xref>.{N, Z, C, V} condition flags.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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<para>When these settings permit the execution of Advanced SIMD and floating-point instructions, if the specified floating-point System register is not the <xref linkend="AArch32.fpscr">FPSCR</xref>, the instruction is <arm-defined-word>undefined</arm-defined-word> if executed in User mode.</para>
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<para>In an implementation that includes EL2, when <xref linkend="AArch32.hcr">HCR</xref>.TID0 is set to 1, any <instruction>VMRS</instruction> access to <xref linkend="AArch32.fpsid">FPSID</xref> from a Non-secure EL1 mode that would be permitted if <xref linkend="AArch32.hcr">HCR</xref>.TID0 was set to 0 generates a Hyp Trap exception. For more information, see <xref linkend="CHDFGEDI">ID group 0, Primary device identification registers</xref>.</para>
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<para>For simplicity, the <instruction>VMRS</instruction> pseudocode does not show the possible trap to Hyp mode.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMRS" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VMRS/T1A1_AS.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="reg" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="7" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="6" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="5" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="2" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="1" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="0" settings="1">
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<c>(0)</c>
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</box>
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</regdiagram>
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<encoding name="VMRS_A1_AS" oneofinclass="1" oneof="2" label="A1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMRS" />
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</docvars>
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<asmtemplate><text>VMRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose destination register (field "Rt")"><Rt></a><text>, </text><a link="sa_spec_reg" hover="Source Advanced SIMD and floating-point System register (field "reg")"><spec_reg></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMRS/T1A1_AS.txt" mylink="aarch32.instrs.VMRS.T1A1_AS.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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if !(reg IN {'000x', '0101', '011x', '1000'}) then UNPREDICTABLE;
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if t == 15 && reg != '0001' then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">!(reg IN {'000x', '0101', '011x', '1000'})</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction transfers an <arm-defined-word>unknown</arm-defined-word> value to the specified target register. When the Rt field holds the value <value>0b1111</value>, the specified target register is the <xref linkend="AArch32.apsr">APSR</xref>.{N, Z, C, V} bits, and these bits become <arm-defined-word>unknown</arm-defined-word>. Otherwise, the specified target register is the register specified by the <syntax>Rt</syntax> field, R0 - R14.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VMRS" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VMRS/T1A1_AS.txt">
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<box hibit="31" width="11" settings="11">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="reg" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="7" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="6" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="5" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="2" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="1" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="0" settings="1">
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<c>(0)</c>
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</box>
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</regdiagram>
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<encoding name="VMRS_T1_AS" oneofinclass="1" oneof="2" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VMRS" />
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</docvars>
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<asmtemplate><text>VMRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose destination register (field "Rt")"><Rt></a><text>, </text><a link="sa_spec_reg" hover="Source Advanced SIMD and floating-point System register (field "reg")"><spec_reg></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMRS/T1A1_AS.txt" mylink="aarch32.instrs.VMRS.T1A1_AS.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt);
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if !(reg IN {'000x', '0101', '011x', '1000'}) then UNPREDICTABLE;
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if t == 15 && reg != '0001' then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="T1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">!(reg IN {'000x', '0101', '011x', '1000'})</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction transfers an <arm-defined-word>unknown</arm-defined-word> value to the specified target register. When the Rt field holds the value <value>0b1111</value>, the specified target register is the <xref linkend="AArch32.apsr">APSR</xref>.{N, Z, C, V} bits, and these bits become <arm-defined-word>unknown</arm-defined-word>. Otherwise, the specified target register is the register specified by the <syntax>Rt</syntax> field, R0 - R14.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VMRS_A1_AS, VMRS_T1_AS" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMRS_A1_AS, VMRS_T1_AS" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMRS_A1_AS, VMRS_T1_AS" symboldefcount="1">
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<symbol link="sa_rt"><Rt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the general-purpose destination register, encoded in the "Rt" field. Is one of:</para>
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<list type="param">
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<listitem>
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<param>R0-R14</param><content>General-purpose register.</content>
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</listitem>
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<listitem>
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<param>APSR_nzcv</param><content>Permitted only when <syntax><spec_reg></syntax> is <value>FPSCR</value>. Encoded as <binarynumber>0b1111</binarynumber>. The instruction transfers the <xref linkend="AArch32.fpscr">FPSCR</xref>.{N, Z, C, V} condition flags to the <xref linkend="AArch32.apsr">APSR</xref>.{N, Z, C, V} condition flags.</content>
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</listitem>
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</list>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMRS_A1_AS, VMRS_T1_AS" symboldefcount="1">
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<symbol link="sa_spec_reg"><spec_reg></symbol>
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<definition encodedin="reg">
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<intro>Is the source Advanced SIMD and floating-point System register, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">reg</entry>
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<entry class="symbol"><spec_reg></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0000</entry>
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<entry class="symbol">FPSID</entry>
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</row>
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<row>
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<entry class="bitfield">0001</entry>
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<entry class="symbol">FPSCR</entry>
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</row>
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<row>
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<entry class="bitfield">001x</entry>
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<entry class="symbol">UNPREDICTABLE</entry>
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</row>
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<row>
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<entry class="bitfield">0100</entry>
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<entry class="symbol">UNPREDICTABLE</entry>
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</row>
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<row>
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<entry class="bitfield">0101</entry>
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<entry class="symbol">MVFR2</entry>
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</row>
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<row>
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<entry class="bitfield">0110</entry>
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<entry class="symbol">MVFR1</entry>
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</row>
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<row>
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<entry class="bitfield">0111</entry>
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<entry class="symbol">MVFR0</entry>
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</row>
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<row>
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<entry class="bitfield">1000</entry>
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<entry class="symbol">FPEXC</entry>
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</row>
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<row>
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<entry class="bitfield">1001</entry>
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<entry class="symbol">UNPREDICTABLE</entry>
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</row>
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<row>
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<entry class="bitfield">101x</entry>
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<entry class="symbol">UNPREDICTABLE</entry>
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</row>
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<row>
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<entry class="bitfield">11xx</entry>
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<entry class="symbol">UNPREDICTABLE</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMRS/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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if reg == '0001' then // FPSCR
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<a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);
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if t == 15 then
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PSTATE.<N,Z,C,V> = FPSR.<N,Z,C,V>;
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else
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = FPSCR;
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elsif PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then
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UNDEFINED; // Non-FPSCR registers accessible only at PL1 or above
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else
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<a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(FALSE); // Non-FPSCR registers are not affected by FPEXC.EN
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<a link="AArch32.CheckAdvSIMDOrFPRegisterTraps.1" file="shared_pseudocode.xml" hover="function: AArch32.CheckAdvSIMDOrFPRegisterTraps(bits(4) reg)">AArch32.CheckAdvSIMDOrFPRegisterTraps</a>(reg);
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case reg of
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when '0000' <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = FPSID;
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when '0101' <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = MVFR2;
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when '0110' <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = MVFR1;
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when '0111' <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = MVFR0;
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when '1000' <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = FPEXC;
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otherwise <a link="impl-shared.Unreachable.0" file="shared_pseudocode.xml" hover="function: Unreachable()">Unreachable</a>(); // Dealt with above or in encoding-specific pseudocode</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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