293 lines
16 KiB
XML
293 lines
16 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VMOV_sr" title="VMOV (scalar to general-purpose register) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VMOV" />
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</docvars>
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<heading>VMOV (scalar to general-purpose register)</heading>
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<desc>
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<brief>
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<para>Copy a vector element to a general-purpose register with sign or zero extension</para>
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</brief>
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<authored>
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<para>Copy a vector element to a general-purpose register with sign or zero extension copies a byte, halfword, or word from an Advanced SIMD scalar to a general-purpose register. Bytes and halfwords can be either zero-extended or sign-extended.</para>
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<para>On a Floating-point-only system, this instruction transfers one word from the upper or lower half of a double-precision floating-point register to a general-purpose register. This is an identical operation to the Advanced SIMD single word transfer.</para>
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<para>For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VMOV_sr/T1A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" width="2" name="opc1" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" width="2" name="opc2" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="2" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="1" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="0" settings="1">
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<c>(0)</c>
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</box>
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</regdiagram>
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<encoding name="VMOV_sr_A1" oneofinclass="1" oneof="2" label="A1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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</docvars>
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<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="The data type"><dt></a><text>}</text><text> </text><a link="sa_rt" hover="The destination general-purpose register"><Rt></a><text>, </text><a link="sa_dn_x" hover="The scalar"><Dn[x]></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMOV_sr/T1A1_A.txt" mylink="aarch32.instrs.VMOV_sr.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean advsimd;
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integer esize;
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integer index;
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case U:opc1:opc2 of
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when 'x1xxx' advsimd = TRUE; esize = 8; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1<0>:opc2);
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when 'x0xx1' advsimd = TRUE; esize = 16; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1<0>:opc2<1>);
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when '00x00' advsimd = FALSE; esize = 32; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1<0>);
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when '10x00' UNDEFINED;
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when 'x0x10' UNDEFINED;
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t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); unsigned = (U == '1');
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if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VMOV" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VMOV_sr/T1A1_A.txt">
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<box hibit="31" width="8" settings="8">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" width="2" name="opc1" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" width="2" name="opc2" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="2" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="1" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="0" settings="1">
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<c>(0)</c>
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</box>
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</regdiagram>
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<encoding name="VMOV_sr_T1" oneofinclass="1" oneof="2" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VMOV" />
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</docvars>
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<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_dt" hover="The data type"><dt></a><text>}</text><text> </text><a link="sa_rt" hover="The destination general-purpose register"><Rt></a><text>, </text><a link="sa_dn_x" hover="The scalar"><Dn[x]></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMOV_sr/T1A1_A.txt" mylink="aarch32.instrs.VMOV_sr.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean advsimd;
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integer esize;
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integer index;
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case U:opc1:opc2 of
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when 'x1xxx' advsimd = TRUE; esize = 8; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1<0>:opc2);
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when 'x0xx1' advsimd = TRUE; esize = 16; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1<0>:opc2<1>);
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when '00x00' advsimd = FALSE; esize = 32; index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(opc1<0>);
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when '10x00' UNDEFINED;
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when 'x0x10' UNDEFINED;
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t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); unsigned = (U == '1');
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if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VMOV_sr_A1, VMOV_sr_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMOV_sr_A1, VMOV_sr_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMOV_sr_A1, VMOV_sr_T1" symboldefcount="1">
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<symbol link="sa_dt"><dt></symbol>
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<account encodedin="">
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<intro>
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<para>The data type. It must be one of:</para>
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<list type="param">
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<listitem>
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<param>S8</param><content>Encoded as U = 0, <field>opc1<1></field> = 1. <syntax>[x]</syntax> is encoded in <field>opc1<0></field>, <field>opc2</field>.</content>
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</listitem>
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<listitem>
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<param>S16</param><content>Encoded as U = 0, <field>opc1<1></field> = 0, <field>opc2<0></field> = 1. <syntax>[x]</syntax> is encoded in <field>opc1<0></field>, <field>opc2<1></field>.</content>
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</listitem>
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<listitem>
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<param>U8</param><content>Encoded as U = 1, <field>opc1<1></field> = 1. <syntax>[x]</syntax> is encoded in <field>opc1<0></field>, <field>opc2</field>.</content>
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</listitem>
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<listitem>
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<param>U16</param><content>Encoded as U = 1, <field>opc1<1></field> = 0, <field>opc2<0></field> = 1. <syntax>[x]</syntax> is encoded in <field>opc1<0></field>, <field>opc2<1></field>.</content>
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</listitem>
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<listitem>
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<param>32</param><content>Encoded as U = 0, <field>opc1<1></field> = 0, <field>opc2</field> = <binarynumber>0b00</binarynumber>. <syntax>[x]</syntax> is encoded in <field>opc1<0></field>.</content>
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</listitem>
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<listitem>
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<param>omitted</param><content>Equivalent to <value>32</value>.</content>
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</listitem>
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</list>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMOV_sr_A1, VMOV_sr_T1" symboldefcount="1">
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<symbol link="sa_rt"><Rt></symbol>
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<account encodedin="">
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<intro>
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<para>The destination general-purpose register.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMOV_sr_A1, VMOV_sr_T1" symboldefcount="1">
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<symbol link="sa_dn_x"><Dn[x]></symbol>
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<account encodedin="">
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<intro>
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<para>The scalar. For details of how <syntax>[x]</syntax> is encoded see the description of <syntax><dt></syntax>.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMOV_sr/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);
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if unsigned then
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],index,esize], 32);
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else
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n],index,esize], 32);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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