1225 lines
63 KiB
XML
1225 lines
63 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VMOV_i" title="VMOV (immediate) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VMOV" />
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</docvars>
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<heading>VMOV (immediate)</heading>
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<desc>
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<brief>
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<para>Copy immediate value to a SIMD&FP register</para>
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</brief>
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<authored>
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<para>Copy immediate value to a SIMD&FP register places an immediate constant into every element of the destination register.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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<encodingnotes>
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<para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="10">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>, </txt>
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<a href="#iclass_a2">A2</a>
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<txt>, </txt>
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<a href="#iclass_a3">A3</a>
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<txt>, </txt>
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<a href="#iclass_a4">A4</a>
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<txt> and </txt>
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<a href="#iclass_a5">A5</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>, </txt>
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<a href="#iclass_t2">T2</a>
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<txt>, </txt>
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<a href="#iclass_t3">T3</a>
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<txt>, </txt>
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<a href="#iclass_t4">T4</a>
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<txt> and </txt>
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<a href="#iclass_t5">T5</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="10" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VMOV_i/T1A1_A.txt" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" name="i" usename="1">
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<c></c>
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</box>
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<box hibit="23" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="18" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="cmode" usename="1" settings="2">
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<c>0</c>
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<c>x</c>
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<c>x</c>
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<c>0</c>
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</box>
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<box hibit="7" settings="1">
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<c>0</c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="op" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="imm4" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VMOV_i_A1_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
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</encoding>
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<encoding name="VMOV_i_A1_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMOV_i/T1A1_A.txt" mylink="aarch32.instrs.VMOV_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)";
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if op == '1' && cmode != '1110' then SEE "Related encodings";
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if Q == '1' && Vd<0> == '1' then UNDEFINED;
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single_register = FALSE; advsimd = TRUE; imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="A2" oneof="10" id="iclass_a2" no_encodings="3" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VMOV_i/A2_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="imm4H" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="7" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="6" settings="1">
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<c>0</c>
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</box>
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<box hibit="5" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="imm4L" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VMOV_i_A2_H" oneofinclass="3" oneof="22" label="Half-precision scalar" bitdiffs="size == 01">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="fpdatasize" value="halfprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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<docvar key="mnemonic-fpdatasize" value="VMOV-halfprec" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="9" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field "imm4H:imm4L")"><imm></a></asmtemplate>
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</encoding>
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<encoding name="VMOV_i_A2_S" oneofinclass="3" oneof="22" label="Single-precision scalar" bitdiffs="size == 10">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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<docvar key="mnemonic-fpdatasize" value="VMOV-singleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field "imm4H:imm4L")"><imm></a></asmtemplate>
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</encoding>
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<encoding name="VMOV_i_A2_D" oneofinclass="3" oneof="22" label="Double-precision scalar" bitdiffs="size == 11">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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<docvar key="mnemonic-fpdatasize" value="VMOV-doubleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field "imm4H:imm4L")"><imm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMOV_i/A2_A.txt" mylink="aarch32.instrs.VMOV_i.A2_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
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if size == '00' || (size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
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if size == '01' && cond != '1110' then UNPREDICTABLE;
|
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single_register = (size != '11'); advsimd = FALSE;
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bits(16) imm16;
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bits(32) imm32;
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bits(64) imm64;
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integer d;
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integer regs;
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case size of
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when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); imm16 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 16); imm32 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : imm16;
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|
when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); imm32 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 32);
|
|
when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); imm64 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 64); regs = 1;</pstext>
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</ps>
|
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</ps_section>
|
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<constrained_unpredictables encoding="A2" ps_block="Decode">
|
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<cu_case>
|
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<cu_cause>
|
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<pstext mayhavelinks="1">size == '01' && cond != '1110'</pstext>
|
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</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
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</cu_type>
|
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<cu_type>
|
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<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
|
|
</cu_type>
|
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<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</iclass>
|
|
<iclass name="A3" oneof="10" id="iclass_a3" no_encodings="2" isa="A32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
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<docvar key="mnemonic" value="VMOV" />
|
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</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
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<regdiagram form="32" psname="aarch32/instrs/VMOV_i/T3A3_A.txt" tworows="1">
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|
<box hibit="31" width="7" settings="7">
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<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="24" name="i" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="cmode" usename="1" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>x</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="6" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VMOV_i_A3_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="double" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I16 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VMOV_i_A3_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I16 </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VMOV_i/T3A3_A.txt" mylink="aarch32.instrs.VMOV_i.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)";
|
|
if op == '1' && cmode != '1110' then SEE "Related encodings";
|
|
if Q == '1' && Vd<0> == '1' then UNDEFINED;
|
|
single_register = FALSE; advsimd = TRUE; imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="A4" oneof="10" id="iclass_a4" no_encodings="2" isa="A32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A4" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="32" psname="aarch32/instrs/VMOV_i/T4A4_A.txt" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="24" name="i" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="cmode" usename="1" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>x</c>
|
|
<c>x</c>
|
|
</box>
|
|
<box hibit="7" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="6" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VMOV_i_A4_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A4" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="double" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="The data type (field "cmode") [F32,I8,I32]"><dt></a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VMOV_i_A4_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A4" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="The data type (field "cmode") [F32,I8,I32]"><dt></a><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VMOV_i/T4A4_A.txt" mylink="aarch32.instrs.VMOV_i.T4A4_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)";
|
|
if op == '1' && cmode != '1110' then SEE "Related encodings";
|
|
if Q == '1' && Vd<0> == '1' then UNDEFINED;
|
|
single_register = FALSE; advsimd = TRUE; imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="A5" oneof="10" id="iclass_a5" no_encodings="2" isa="A32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A5" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="32" psname="aarch32/instrs/VMOV_i/T5A5_A.txt" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="24" name="i" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="cmode" usename="1" settings="4">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="6" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VMOV_i_A5_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A5" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="double" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VMOV_i_A5_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A5" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I64 </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VMOV_i/T5A5_A.txt" mylink="aarch32.instrs.VMOV_i.T5A5_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)";
|
|
if op == '1' && cmode != '1110' then SEE "Related encodings";
|
|
if Q == '1' && Vd<0> == '1' then UNDEFINED;
|
|
single_register = FALSE; advsimd = TRUE; imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T1" oneof="10" id="iclass_t1" no_encodings="2" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VMOV_i/T1A1_A.txt" tworows="1">
|
|
<box hibit="31" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="28" name="i" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="27" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="cmode" usename="1" settings="2">
|
|
<c>0</c>
|
|
<c>x</c>
|
|
<c>x</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="6" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VMOV_i_T1_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="double" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I32 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VMOV_i_T1_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I32 </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VMOV_i/T1A1_A.txt" mylink="aarch32.instrs.VMOV_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)";
|
|
if op == '1' && cmode != '1110' then SEE "Related encodings";
|
|
if Q == '1' && Vd<0> == '1' then UNDEFINED;
|
|
single_register = FALSE; advsimd = TRUE; imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T2" oneof="10" id="iclass_t2" no_encodings="3" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
</docvars>
|
|
<iclassintro count="3"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VMOV_i/T2_A.txt">
|
|
<box hibit="31" width="9" settings="9">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="imm4H" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="7" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="6" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="imm4L" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VMOV_i_T2_H" oneofinclass="3" oneof="22" label="Half-precision scalar" bitdiffs="size == 01">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="fpdatasize" value="halfprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="mnemonic-fpdatasize" value="VMOV-halfprec" />
|
|
</docvars>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
|
|
</arch_variants>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field "imm4H:imm4L")"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VMOV_i_T2_S" oneofinclass="3" oneof="22" label="Single-precision scalar" bitdiffs="size == 10">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="fpdatasize" value="singleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="mnemonic-fpdatasize" value="VMOV-singleprec" />
|
|
</docvars>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field "imm4H:imm4L")"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VMOV_i_T2_D" oneofinclass="3" oneof="22" label="Double-precision scalar" bitdiffs="size == 11">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="fpdatasize" value="doubleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="mnemonic-fpdatasize" value="VMOV-doubleprec" />
|
|
</docvars>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm_1" hover="Signed floating-point constant with 3-bit exponent and normalized 4 bits of precision (field "imm4H:imm4L")"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VMOV_i/T2_A.txt" mylink="aarch32.instrs.VMOV_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
|
|
if size == '00' || (size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
|
|
if size == '01' && <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
|
|
single_register = (size != '11'); advsimd = FALSE;
|
|
bits(16) imm16;
|
|
bits(32) imm32;
|
|
bits(64) imm64;
|
|
integer d;
|
|
integer regs;
|
|
case size of
|
|
when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); imm16 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 16); imm32 = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : imm16;
|
|
when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); imm32 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 32);
|
|
when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); imm64 = <a link="impl-shared.VFPExpandImm.2" file="shared_pseudocode.xml" hover="function: bits(N) VFPExpandImm(bits(8) imm8, integer N)">VFPExpandImm</a>(imm4H:imm4L, 64); regs = 1;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<constrained_unpredictables encoding="T2" ps_block="Decode">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">size == '01' && InITBlock()</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
|
|
</cu_type>
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
|
|
</cu_type>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</iclass>
|
|
<iclass name="T3" oneof="10" id="iclass_t3" no_encodings="2" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VMOV_i/T3A3_A.txt" tworows="1">
|
|
<box hibit="31" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="28" name="i" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="27" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="cmode" usename="1" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>x</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="6" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VMOV_i_T3_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="double" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I16 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VMOV_i_T3_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I16 </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VMOV_i/T3A3_A.txt" mylink="aarch32.instrs.VMOV_i.T3A3_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)";
|
|
if op == '1' && cmode != '1110' then SEE "Related encodings";
|
|
if Q == '1' && Vd<0> == '1' then UNDEFINED;
|
|
single_register = FALSE; advsimd = TRUE; imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T4" oneof="10" id="iclass_t4" no_encodings="2" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T4" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VMOV_i/T4A4_A.txt" tworows="1">
|
|
<box hibit="31" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="28" name="i" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="27" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="cmode" usename="1" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>x</c>
|
|
<c>x</c>
|
|
</box>
|
|
<box hibit="7" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="6" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VMOV_i_T4_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T4" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="double" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="The data type (field "cmode") [F32,I8,I32]"><dt></a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VMOV_i_T4_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T4" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="The data type (field "cmode") [F32,I8,I32]"><dt></a><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VMOV_i/T4A4_A.txt" mylink="aarch32.instrs.VMOV_i.T4A4_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)";
|
|
if op == '1' && cmode != '1110' then SEE "Related encodings";
|
|
if Q == '1' && Vd<0> == '1' then UNDEFINED;
|
|
single_register = FALSE; advsimd = TRUE; imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T5" oneof="10" id="iclass_t5" no_encodings="2" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T5" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VMOV_i/T5A5_A.txt" tworows="1">
|
|
<box hibit="31" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="28" name="i" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="27" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="cmode" usename="1" settings="4">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="6" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="op" usename="1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VMOV_i_T5_D" oneofinclass="2" oneof="22" label="64-bit SIMD vector" bitdiffs="Q == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T5" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="double" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VMOV_i_T5_Q" oneofinclass="2" oneof="22" label="128-bit SIMD vector" bitdiffs="Q == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T5" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VMOV" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I64 </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VMOV_i/T5A5_A.txt" mylink="aarch32.instrs.VMOV_i.T5A5_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if op == '0' && cmode<0> == '1' && cmode<3:2> != '11' then SEE "VORR (immediate)";
|
|
if op == '1' && cmode != '1110' then SEE "Related encodings";
|
|
if Q == '1' && Vd<0> == '1' then UNDEFINED;
|
|
single_register = FALSE; advsimd = TRUE; imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>(op, cmode, i:imm3:imm4);
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="VMOV_i_A1_Q, VMOV_i_A3_Q, VMOV_i_A4_Q, VMOV_i_A5_Q" symboldefcount="1">
|
|
<symbol link="sa_c_1"><c></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1, A3, A4 and A5: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VMOV_i_A2_H, VMOV_i_T1_Q, VMOV_i_T2_H, VMOV_i_T3_Q, VMOV_i_T4_Q, VMOV_i_T5_Q" symboldefcount="2">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>For encoding A2, T1, T2, T3, T4 and T5: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VMOV_i_A1_Q, VMOV_i_A2_H, VMOV_i_A3_Q, VMOV_i_A4_Q, VMOV_i_A5_Q, VMOV_i_T1_Q, VMOV_i_T2_H, VMOV_i_T3_Q, VMOV_i_T4_Q, VMOV_i_T5_Q" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VMOV_i_A4_Q, VMOV_i_T4_Q" symboldefcount="1">
|
|
<symbol link="sa_dt"><dt></symbol>
|
|
<definition encodedin="cmode">
|
|
<intro>The data type, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">cmode</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">110x</entry>
|
|
<entry class="symbol">I32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1110</entry>
|
|
<entry class="symbol">I8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1111</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="VMOV_i_A1_Q, VMOV_i_A3_Q, VMOV_i_A4_Q, VMOV_i_A5_Q, VMOV_i_T1_Q, VMOV_i_T3_Q, VMOV_i_T4_Q, VMOV_i_T5_Q" symboldefcount="1">
|
|
<symbol link="sa_qd"><Qd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VMOV_i_A1_D, VMOV_i_A2_D, VMOV_i_A3_D, VMOV_i_A4_D, VMOV_i_A5_D, VMOV_i_T1_D, VMOV_i_T2_D, VMOV_i_T3_D, VMOV_i_T4_D, VMOV_i_T5_D" symboldefcount="1">
|
|
<symbol link="sa_dd"><Dd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VMOV_i_A2_H, VMOV_i_T2_H" symboldefcount="1">
|
|
<symbol link="sa_sd"><Sd></symbol>
|
|
<account encodedin="Vd:D">
|
|
<intro>
|
|
<para>Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VMOV_i_A1_Q, VMOV_i_A3_Q, VMOV_i_A4_Q, VMOV_i_A5_Q, VMOV_i_T1_Q, VMOV_i_T3_Q, VMOV_i_T4_Q, VMOV_i_T5_Q" symboldefcount="1">
|
|
<symbol link="sa_imm"><imm></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1, A3, A4, A5, T1, T3, T4 and T5: is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <syntax><imm></syntax>, see <xref linkend="CJAIDJDJ">Modified immediate constants in T32 and A32 Advanced SIMD instructions</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VMOV_i_A2_H, VMOV_i_T2_H" symboldefcount="2">
|
|
<symbol link="sa_imm_1"><imm></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="fpdatasize" value="halfprec" />
|
|
<docvar key="mnemonic-fpdatasize" value="VMOV-halfprec" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A2 and T2: is a signed floating-point constant with 3-bit exponent and normalized 4 bits of precision, encoded in "imm4H:imm4L". For details of the range of constants available and the encoding of <syntax><imm></syntax>, see <xref linkend="CJAJBHCG">Modified immediate constants in T32 and A32 floating-point instructions</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VMOV_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);
|
|
if single_register then
|
|
<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = imm32;
|
|
else
|
|
for r = 0 to regs-1
|
|
<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = imm64;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|