317 lines
17 KiB
XML
317 lines
17 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VMOV_h" title="VMOV (between general-purpose register and half-precision) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VMOV" />
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</docvars>
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<heading>VMOV (between general-purpose register and half-precision)</heading>
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<desc>
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<brief>
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<para>Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register</para>
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</brief>
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<authored>
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<para>Copy 16 bits of a general-purpose register to or from a 32-bit SIMD&FP register. This instruction transfers the value held in the bottom 16 bits of a 32-bit SIMD&FP register to the bottom 16 bits of a general-purpose register, or the value held in the bottom 16 bits of a general-purpose register to the bottom 16 bits of a 32-bit SIMD&FP register.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<regdiagram form="32" psname="aarch32/instrs/VMOV_h/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" name="op" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="5" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="2" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="1" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="0" settings="1">
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<c>(0)</c>
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</box>
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</regdiagram>
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<encoding name="VMOV_toh_A1" oneofinclass="2" oneof="4" label="From general-purpose register" bitdiffs="op == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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<docvar key="to-or-from-gp" value="from-gp" />
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</docvars>
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<box hibit="20" width="1" name="op">
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<c>0</c>
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</box>
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<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_sn" hover="32-bit SIMD&FP register to be transferred (field "Vn:N")"><Sn></a><text>, </text><a link="sa_rt" hover="General-purpose register that {syntax{<Sn>}} will be transferred to or from (field "Rt")"><Rt></a></asmtemplate>
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</encoding>
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<encoding name="VMOV_h_A1" oneofinclass="2" oneof="4" label="To general-purpose register" bitdiffs="op == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMOV" />
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<docvar key="to-or-from-gp" value="to-gp" />
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</docvars>
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<box hibit="20" width="1" name="op">
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<c>1</c>
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</box>
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<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_rt" hover="General-purpose register that {syntax{<Sn>}} will be transferred to or from (field "Rt")"><Rt></a><text>, </text><a link="sa_sn" hover="32-bit SIMD&FP register to be transferred (field "Vn:N")"><Sn></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMOV_h/A1_A.txt" mylink="aarch32.instrs.VMOV_h.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
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if cond != '1110' then UNPREDICTABLE;
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to_arm_register = (op == '1'); t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);
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if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">cond != '1110'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type>
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<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
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</cu_type>
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<cu_type>
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<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VMOV" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<regdiagram form="16x2" psname="aarch32/instrs/VMOV_h/T1_A.txt">
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<box hibit="31" width="11" settings="11">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" name="op" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="5" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="2" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="1" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="0" settings="1">
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<c>(0)</c>
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</box>
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</regdiagram>
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<encoding name="VMOV_toh_T1" oneofinclass="2" oneof="4" label="From general-purpose register" bitdiffs="op == 0">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VMOV" />
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<docvar key="to-or-from-gp" value="from-gp" />
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</docvars>
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<box hibit="20" width="1" name="op">
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<c>0</c>
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</box>
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<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_sn" hover="32-bit SIMD&FP register to be transferred (field "Vn:N")"><Sn></a><text>, </text><a link="sa_rt" hover="General-purpose register that {syntax{<Sn>}} will be transferred to or from (field "Rt")"><Rt></a></asmtemplate>
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</encoding>
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<encoding name="VMOV_h_T1" oneofinclass="2" oneof="4" label="To general-purpose register" bitdiffs="op == 1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VMOV" />
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<docvar key="to-or-from-gp" value="to-gp" />
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</docvars>
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<box hibit="20" width="1" name="op">
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<c>1</c>
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</box>
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<asmtemplate><text>VMOV</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_rt" hover="General-purpose register that {syntax{<Sn>}} will be transferred to or from (field "Rt")"><Rt></a><text>, </text><a link="sa_sn" hover="32-bit SIMD&FP register to be transferred (field "Vn:N")"><Sn></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMOV_h/T1_A.txt" mylink="aarch32.instrs.VMOV_h.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
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if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
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to_arm_register = (op == '1'); t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);
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if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="T1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">InITBlock()</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type>
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<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
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</cu_type>
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<cu_type>
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<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
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<symbol link="sa_rt"><Rt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the general-purpose register that <syntax><Sn></syntax> will be transferred to or from, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
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<symbol link="sa_sn"><Sn></symbol>
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<account encodedin="Vn:N">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Vn:N" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMOV_h_A1, VMOV_toh_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMOV_h/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);
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if to_arm_register then
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]<15:0>;
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else
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<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[n] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]<15:0>;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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