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slonik/specs/vmmla.xml

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="VMMLA" title="VMMLA -- AArch32" type="instruction">
<docvars>
<docvar key="instr-class" value="fpsimd" />
<docvar key="mnemonic" value="VMMLA" />
<docvar key="simdvectorsize" value="quad" />
</docvars>
<heading>VMMLA</heading>
<desc>
<brief>
<para>BFloat16 floating-point matrix multiply-accumulate</para>
</brief>
<authored>
<para>BFloat16 floating-point matrix multiply-accumulate. This instruction multiplies the 2x4 matrix of BF16 values in the first 128-bit source vector by the 4x2 BF16 matrix in the second 128-bit source vector. The resulting 2x2 single-precision matrix product is then added destructively to the 2x2 single-precision matrix in the 128-bit destination vector. This is equivalent to performing a 4-way dot product per destination element. The instruction does not update the <xref linkend="AArch32.fpscr">FPSCR</xref> exception status.</para>
<note>
<para>Arm expects that the VMMLA instruction will deliver a peak BF16 multiply throughput that is at least as high as can be achieved using two VDOT instructions, with a goal that it should have significantly higher throughput.</para>
</note>
</authored>
</desc>
<alias_list howmany="0"></alias_list>
<classes>
<classesintro count="2">
<txt>It has encodings from the following instruction sets:</txt>
<txt> A32 (</txt>
<a href="#iclass_a1">A1</a>
<txt>)</txt>
<txt> and </txt>
<txt> T32 (</txt>
<a href="#iclass_t1">T1</a>
<txt>)</txt>
<txt>.</txt>
</classesintro>
<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
<docvars>
<docvar key="armarmheading" value="A1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="A32" />
<docvar key="mnemonic" value="VMMLA" />
<docvar key="simdvectorsize" value="quad" />
</docvars>
<iclassintro count="1"></iclassintro>
<arch_variants>
<arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
</arch_variants>
<regdiagram form="32" psname="aarch32/instrs/VMMLA/A1_A.txt">
<box hibit="31" width="7" settings="7">
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="24" width="2" name="op1" settings="2">
<c>0</c>
<c>0</c>
</box>
<box hibit="22" name="D" usename="1">
<c></c>
</box>
<box hibit="21" name="op" settings="1">
<c>0</c>
</box>
<box hibit="20" name="sz" settings="1">
<c>0</c>
</box>
<box hibit="19" width="4" name="Vn" usename="1">
<c colspan="4"></c>
</box>
<box hibit="15" width="4" name="Vd" usename="1">
<c colspan="4"></c>
</box>
<box hibit="11" settings="1">
<c>1</c>
</box>
<box hibit="10" name="op3" settings="1">
<c>1</c>
</box>
<box hibit="9" settings="1">
<c>0</c>
</box>
<box hibit="8" name="op4" settings="1">
<c>0</c>
</box>
<box hibit="7" name="N" usename="1">
<c></c>
</box>
<box hibit="6" name="Q" settings="1">
<c>1</c>
</box>
<box hibit="5" name="M" usename="1">
<c></c>
</box>
<box hibit="4" name="U" settings="1">
<c>0</c>
</box>
<box hibit="3" width="4" name="Vm" usename="1">
<c colspan="4"></c>
</box>
</regdiagram>
<encoding name="VMMLA_A1_Q" oneofinclass="1" oneof="2" label="A1">
<docvars>
<docvar key="armarmheading" value="A1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="A32" />
<docvar key="mnemonic" value="VMMLA" />
<docvar key="simdvectorsize" value="quad" />
</docvars>
<asmtemplate><text>VMMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="aarch32/instrs/VMMLA/A1_A.txt" mylink="aarch32.instrs.VMMLA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;
if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
integer regs = 2;</pstext>
</ps>
</ps_section>
</iclass>
<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
<docvars>
<docvar key="armarmheading" value="T1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="T32" />
<docvar key="mnemonic" value="VMMLA" />
<docvar key="simdvectorsize" value="quad" />
</docvars>
<iclassintro count="1"></iclassintro>
<arch_variants>
<arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
</arch_variants>
<regdiagram form="16x2" psname="aarch32/instrs/VMMLA/T1_A.txt">
<box hibit="31" width="7" settings="7">
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="24" width="2" name="op1" settings="2">
<c>0</c>
<c>0</c>
</box>
<box hibit="22" name="D" usename="1">
<c></c>
</box>
<box hibit="21" name="op" settings="1">
<c>0</c>
</box>
<box hibit="20" name="sz" settings="1">
<c>0</c>
</box>
<box hibit="19" width="4" name="Vn" usename="1">
<c colspan="4"></c>
</box>
<box hibit="15" width="4" name="Vd" usename="1">
<c colspan="4"></c>
</box>
<box hibit="11" settings="1">
<c>1</c>
</box>
<box hibit="10" name="op3" settings="1">
<c>1</c>
</box>
<box hibit="9" settings="1">
<c>0</c>
</box>
<box hibit="8" name="op4" settings="1">
<c>0</c>
</box>
<box hibit="7" name="N" usename="1">
<c></c>
</box>
<box hibit="6" name="Q" settings="1">
<c>1</c>
</box>
<box hibit="5" name="M" usename="1">
<c></c>
</box>
<box hibit="4" name="U" settings="1">
<c>0</c>
</box>
<box hibit="3" width="4" name="Vm" usename="1">
<c colspan="4"></c>
</box>
</regdiagram>
<encoding name="VMMLA_T1_Q" oneofinclass="1" oneof="2" label="T1">
<docvars>
<docvar key="armarmheading" value="T1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="T32" />
<docvar key="mnemonic" value="VMMLA" />
<docvar key="simdvectorsize" value="quad" />
</docvars>
<asmtemplate><text>VMMLA</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="aarch32/instrs/VMMLA/T1_A.txt" mylink="aarch32.instrs.VMMLA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;
if Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1' then UNDEFINED;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
integer regs = 2;</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="VMMLA_A1_Q, VMMLA_T1_Q" symboldefcount="1">
<symbol link="sa_q">&lt;q&gt;</symbol>
<account encodedin="">
<intro>
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
</intro>
</account>
</explanation>
<explanation enclist="VMMLA_A1_Q, VMMLA_T1_Q" symboldefcount="1">
<symbol link="sa_qd">&lt;Qd&gt;</symbol>
<account encodedin="D:Vd">
<intro>
<para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
</intro>
</account>
</explanation>
<explanation enclist="VMMLA_A1_Q, VMMLA_T1_Q" symboldefcount="1">
<symbol link="sa_qn">&lt;Qn&gt;</symbol>
<account encodedin="N:Vn">
<intro>
<para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
</intro>
</account>
</explanation>
<explanation enclist="VMMLA_A1_Q, VMMLA_T1_Q" symboldefcount="1">
<symbol link="sa_qm">&lt;Qm&gt;</symbol>
<account encodedin="M:Vm">
<intro>
<para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="aarch32/instrs/VMMLA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
bits(128) op1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n&gt;&gt;1];
bits(128) op2 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m&gt;&gt;1];
bits(128) acc = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d&gt;&gt;1];
<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d&gt;&gt;1] = <a link="impl-shared.BFMatMulAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) BFMatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2)">BFMatMulAdd</a>(acc, op1, op2);</pstext>
</ps>
</ps_section>
</instructionsection>
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