419 lines
26 KiB
XML
419 lines
26 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VMLS_s" title="VMLS (by scalar) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VMLS" />
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</docvars>
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<heading>VMLS (by scalar)</heading>
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<desc>
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<brief>
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<para>Vector Multiply Subtract (by scalar)</para>
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</brief>
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<authored>
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<para>Vector Multiply Subtract multiplies elements of a vector by a scalar, and either subtracts the products from corresponding elements of the destination vector.</para>
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<para>For more information about scalars see <xref linkend="Cjaibjhd">Advanced SIMD scalars</xref>.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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<encodingnotes>
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<para>Related encodings: See <xref linkend="T32.encoding_index.simddp">Advanced SIMD data-processing</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.advsimddp">Advanced SIMD data-processing</xref> for the A32 instruction set.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1 and this instruction passes its condition execution check and is operating only on integer vector elements, then the following apply:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMLS" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VMLA_s/A1_A.txt" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="23" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
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<c colspan="2">!= 11</c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" settings="1">
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<c>0</c>
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</box>
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<box hibit="10" name="op" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" settings="1">
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<c>0</c>
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</box>
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<box hibit="8" name="F" usename="1">
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<c></c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" settings="1">
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<c>1</c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VMLS_s_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMLS" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="24" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VMLS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field "F:size")"><dt></a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP register holding accumulate vector (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&FP source register holding scalar (field "Vm<2:0>")"><Dm[x]></a></asmtemplate>
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</encoding>
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<encoding name="VMLS_s_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VMLS" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="24" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VMLS</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field "F:size")"><dt></a><text> </text><a link="sa_qd" hover="128-bit SIMD&FP register holding accumulate vector (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&FP source register (field "N:Vn")"><Qn></a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&FP source register holding scalar (field "Vm<2:0>")"><Dm[x]></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMLA_s/A1_A.txt" mylink="aarch32.instrs.VMLA_s.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' then SEE "Related encodings";
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if size == '00' || (F == '1' && size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
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if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED;
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unsigned = FALSE; // "Don't care" value: TRUE produces same functionality
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add = (op == '0'); floating_point = (F == '1'); long_destination = FALSE;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); regs = if Q == '0' then 1 else 2;
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integer esize;
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integer elements;
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integer m;
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integer index;
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if size == '01' then esize = 16; elements = 4; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm<2:0>); index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm<3>);
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if size == '10' then esize = 32; elements = 2; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm); index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VMLS" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VMLA_s/T1_A.txt" tworows="1">
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<box hibit="31" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="28" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="size" usename="1" settings="2" constraint="!= 11">
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<c colspan="2">!= 11</c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" settings="1">
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<c>0</c>
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</box>
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<box hibit="10" name="op" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="9" settings="1">
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<c>0</c>
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</box>
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<box hibit="8" name="F" usename="1">
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<c></c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" settings="1">
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<c>1</c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VMLS_s_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VMLS" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="28" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field "F:size")"><dt></a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP register holding accumulate vector (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&FP source register holding scalar (field "Vm<2:0>")"><Dm[x]></a></asmtemplate>
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</encoding>
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<encoding name="VMLS_s_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VMLS" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="28" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VMLS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for scalar and the elements of operand vector (field "F:size")"><dt></a><text> </text><a link="sa_qd" hover="128-bit SIMD&FP register holding accumulate vector (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&FP source register (field "N:Vn")"><Qn></a><text>, </text><a link="sa_dm_x" hover="Second 64-bit SIMD&FP source register holding scalar (field "Vm<2:0>")"><Dm[x]></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMLA_s/T1_A.txt" mylink="aarch32.instrs.VMLA_s.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' then SEE "Related encodings";
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if size == '00' || (F == '1' && size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
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if F == '1' && size == '01' && <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
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if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED;
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unsigned = FALSE; // "Don't care" value: TRUE produces same functionality
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add = (op == '0'); floating_point = (F == '1'); long_destination = FALSE;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); regs = if Q == '0' then 1 else 2;
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integer esize;
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integer elements;
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integer m;
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integer index;
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if size == '01' then esize = 16; elements = 4; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm<2:0>); index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm<3>);
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if size == '10' then esize = 32; elements = 2; m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm); index = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M);</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="T1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">F == '1' && size == '01' && InITBlock()</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type>
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<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
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</cu_type>
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<cu_type>
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<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
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</cu_type>
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<arch_variants>
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<arch_variant name="ARMv8.2-A" />
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</arch_variants>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VMLS_s_A1_Q" symboldefcount="1">
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<symbol link="sa_c_1"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMLS_s_T1_Q" symboldefcount="2">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMLS_s_A1_Q, VMLS_s_T1_Q" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMLS_s_A1_Q, VMLS_s_T1_Q" symboldefcount="1">
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<symbol link="sa_dt"><dt></symbol>
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<definition encodedin="F:size">
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<intro>Is the data type for the scalar and the elements of the operand vector, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">F</entry>
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<entry class="bitfield">size</entry>
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<entry class="symbol"><dt></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">01</entry>
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<entry class="symbol">I16</entry>
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</row>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">10</entry>
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<entry class="symbol">I32</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="bitfield">01</entry>
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<entry class="symbol">F16</entry>
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</row>
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<row>
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|
<entry class="bitfield">1</entry>
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<entry class="bitfield">10</entry>
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<entry class="symbol">F32</entry>
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</row>
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</tbody>
|
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</tgroup>
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</table>
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</definition>
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<arch_variants>
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<arch_variant name="ARMv8.2-A" />
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</arch_variants>
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</explanation>
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<explanation enclist="VMLS_s_A1_Q, VMLS_s_T1_Q" symboldefcount="1">
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<symbol link="sa_qd"><Qd></symbol>
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<account encodedin="D:Vd">
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<intro>
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<para>Is the 128-bit name of the SIMD&FP register holding the accumulate vector, encoded in the "D:Vd" field as <Qd>*2.</para>
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</intro>
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</account>
|
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</explanation>
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<explanation enclist="VMLS_s_A1_Q, VMLS_s_T1_Q" symboldefcount="1">
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<symbol link="sa_qn"><Qn></symbol>
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<account encodedin="N:Vn">
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<intro>
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<para>Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.</para>
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</intro>
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</account>
|
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</explanation>
|
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<explanation enclist="VMLS_s_A1_D, VMLS_s_T1_D" symboldefcount="1">
|
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<symbol link="sa_dd"><Dd></symbol>
|
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<account encodedin="D:Vd">
|
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<intro>
|
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<para>Is the 64-bit name of the SIMD&FP register holding the accumulate vector, encoded in the "D:Vd" field.</para>
|
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</intro>
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</account>
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</explanation>
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<explanation enclist="VMLS_s_A1_D, VMLS_s_T1_D" symboldefcount="1">
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<symbol link="sa_dn"><Dn></symbol>
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<account encodedin="N:Vn">
|
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<intro>
|
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<para>Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.</para>
|
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</intro>
|
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</account>
|
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</explanation>
|
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<explanation enclist="VMLS_s_A1_Q, VMLS_s_T1_Q" symboldefcount="1">
|
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<symbol link="sa_dm_x"><Dm[x]></symbol>
|
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<account encodedin="">
|
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<intro>
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<para>Is the 64-bit name of the second SIMD&FP source register holding the scalar. If <syntax><dt></syntax> is <value>I16</value> or <value>F16</value>, <syntax>Dm</syntax> is restricted to D0-D7. <syntax>Dm</syntax> is encoded in "Vm<2:0>", and <syntax>x</syntax> is encoded in "M:Vm<3>". If <syntax><dt></syntax> is <value>I32</value> or <value>F32</value>, <syntax>Dm</syntax> is restricted to D0-D15. <syntax>Dm</syntax> is encoded in "Vm", and <syntax>x</syntax> is encoded in "M".</para>
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</intro>
|
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</account>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
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</explanation>
|
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VMLA_s/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
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op2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m],index,esize]; op2val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op2, unsigned);
|
|
for r = 0 to regs-1
|
|
for e = 0 to elements-1
|
|
op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r],e,esize]; op1val = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(op1, unsigned);
|
|
if floating_point then
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fp_addend = (if add then <a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())
|
|
else <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-shared.FPMul.3" file="shared_pseudocode.xml" hover="function: bits(N) FPMul(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMul</a>(op1,op2,<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>())));
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPAdd.3" file="shared_pseudocode.xml" hover="function: bits(N) FPAdd(bits(N) op1, bits(N) op2, FPCRType fpcr)">FPAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize], fp_addend,
|
|
<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());
|
|
else
|
|
addend = if add then op1val*op2val else -op1val*op2val;
|
|
if long_destination then
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d>>1],e,2*esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Qin.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Qin[integer n]">Qin</a>[d>>1],e,2*esize] + addend;
|
|
else
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r],e,esize] + addend;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|