419 lines
27 KiB
XML
419 lines
27 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VLDR_i" title="VLDR (immediate) -- AArch32" type="instruction">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VLDR" />
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</docvars>
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<heading>VLDR (immediate)</heading>
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<desc>
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<brief>
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<para>Load SIMD&FP register (immediate)</para>
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</brief>
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<authored>
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<para>Load SIMD&FP register (immediate) loads a single register from the Advanced SIMD and floating-point register file, using an address from a general-purpose register, with an optional offset.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VLDR" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VLDR/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" settings="1">
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<c>1</c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="W" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="VLDR_A1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="halfprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VLDR" />
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<docvar key="mnemonic-fpdatasize" value="VLDR-halfprec" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="9" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="VLDR_A1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VLDR" />
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<docvar key="mnemonic-fpdatasize" value="VLDR-singleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><a link="sa_32" hover="Optional data size specifier for 32-bit memory accesses that can be used in the assembler source code">{.32}</a><text> </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="VLDR_A1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VLDR" />
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<docvar key="mnemonic-fpdatasize" value="VLDR-doubleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><a link="sa_64" hover="Optional data size specifier for 64-bit memory accesses that can be used in the assembler source code">{.64}</a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VLDR/A1_A.txt" mylink="aarch32.instrs.VLDR.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '00' || (size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
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if size == '01' && cond != '1110' then UNPREDICTABLE;
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esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size); add = (U == '1');
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imm32 = if esize == 16 then <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'0', 32) else <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);
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integer d;
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case size of
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when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);
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when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);
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when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
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n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">size == '01' && cond != '1110'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type>
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<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
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</cu_type>
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<cu_type>
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<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
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</cu_type>
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<arch_variants>
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<arch_variant name="ARMv8.2-A" />
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</arch_variants>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VLDR" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VLDR/T1_A.txt" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" settings="1">
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<c>1</c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="W" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="VLDR_T1_H" oneofinclass="3" oneof="6" label="Half-precision scalar" bitdiffs="size == 01">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="fpdatasize" value="halfprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VLDR" />
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<docvar key="mnemonic-fpdatasize" value="VLDR-halfprec" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="9" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="VLDR_T1_S" oneofinclass="3" oneof="6" label="Single-precision scalar" bitdiffs="size == 10">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VLDR" />
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<docvar key="mnemonic-fpdatasize" value="VLDR-singleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><a link="sa_32" hover="Optional data size specifier for 32-bit memory accesses that can be used in the assembler source code">{.32}</a><text> </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="VLDR_T1_D" oneofinclass="3" oneof="6" label="Double-precision scalar" bitdiffs="size == 11">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VLDR" />
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<docvar key="mnemonic-fpdatasize" value="VLDR-doubleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VLDR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><a link="sa_64" hover="Optional data size specifier for 64-bit memory accesses that can be used in the assembler source code">{.64}</a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VLDR/T1_A.txt" mylink="aarch32.instrs.VLDR.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '00' || (size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
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if size == '01' && <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
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esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size); add = (U == '1');
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imm32 = if esize == 16 then <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'0', 32) else <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);
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integer d;
|
|
case size of
|
|
when '01' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);
|
|
when '10' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D);
|
|
when '11' d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
|
|
n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<constrained_unpredictables encoding="T1" ps_block="Decode">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">size == '01' && InITBlock()</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
|
|
</cu_type>
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
|
|
</cu_type>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLDR_A1_D, VLDR_T1_D" symboldefcount="1">
|
|
<symbol link="sa_64">.64</symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Is an optional data size specifier for 64-bit memory accesses that can be used in the assembler source code, but is otherwise ignored.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLDR_A1_D, VLDR_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dd"><Dd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLDR_A1_S, VLDR_T1_S" symboldefcount="1">
|
|
<symbol link="sa_32">.32</symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Is an optional data size specifier for 32-bit memory accesses that can be used in the assembler source code, but is otherwise ignored.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
|
|
<symbol link="sa_sd"><Sd></symbol>
|
|
<account encodedin="Vd:D">
|
|
<intro>
|
|
<para>Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
|
|
<symbol link="sa_rn"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the general-purpose base register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
|
|
<symbol link="sa__plusminus_">+/-</symbol>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="VLDR_A1_H, VLDR_T1_H" symboldefcount="1">
|
|
<symbol link="sa_imm"><imm></symbol>
|
|
<account encodedin="imm8">
|
|
<intro>
|
|
<para>For the single-precision scalar or double-precision scalar variants: is the optional unsigned immediate byte offset, a multiple of 4, in the range 0 to 1020, defaulting to 0, and encoded in the "imm8" field as <imm>/4.</para>
|
|
<para>For the half-precision scalar variant: is the optional unsigned immediate byte offset, a multiple of 2, in the range 0 to 510, defaulting to 0, and encoded in the "imm8" field as <imm>/2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VLDR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
<a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);
|
|
base = if n == 15 then <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
|
|
address = if add then (base + imm32) else (base - imm32);
|
|
case esize of
|
|
when 16
|
|
<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,2];
|
|
when 32
|
|
<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];
|
|
when 64
|
|
word1 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];
|
|
word2 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];
|
|
// Combine the word-aligned words in the correct order for current endianness.
|
|
<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then word1:word2 else word2:word1;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|