650 lines
41 KiB
XML
650 lines
41 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VLDM" title="VLDM, VLDMDB, VLDMIA -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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</docvars>
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<heading>VLDM, VLDMDB, VLDMIA</heading>
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<desc>
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<brief>
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<para>Load Multiple SIMD&FP registers</para>
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</brief>
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<authored>
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<para>Load Multiple SIMD&FP registers loads multiple registers from consecutive locations in the Advanced SIMD and floating-point register file using an address from a general-purpose register.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGFAHHG">VLDM</xref>.</para>
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<para>Related encodings: See <xref linkend="T32.encoding_index.simdfp_mov64">Advanced SIMD and floating-point 64-bit move</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.movsimdfpgp64">Advanced SIMD and floating-point 64-bit move</xref> for the A32 instruction set.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="1">
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<alias_list_intro>This instruction is used by the alias </alias_list_intro>
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<aliasref aliaspageid="VPOP_VLDM" aliasfile="vpop_vldm.xml" hover="Pop SIMD&FP registers from Stack" punct=".">
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<text>VPOP</text>
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<aliaspref>P == '0' && U == '1' && W == '1' && Rn == '1101'</aliaspref>
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</aliasref>
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<alias_list_outro>
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<text> See </text>
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<aliastablelink />
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<text> below for details of when the alias is preferred.</text>
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</alias_list_outro>
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</alias_list>
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<classes>
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<classesintro count="4">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt> and </txt>
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<a href="#iclass_a2">A2</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t2">T2</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VLDM/T1A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1">
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<c></c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="7" width="7" name="imm8<7:1>" usename="1">
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<c colspan="7"></c>
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</box>
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<box hibit="0" name="imm8<0>" usename="1" settings="1">
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<c>0</c>
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</box>
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</regdiagram>
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<encoding name="VLDMDB_A1" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 && U == 0 && W == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="ldmstm-mode" value="dec-before" />
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<docvar key="mnemonic" value="VLDMDB" />
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<docvar key="mnemonic-fpdatasize" value="VLDMDB-doubleprec" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="23" width="1" name="U">
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<c>0</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>1</c>
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</box>
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<asmtemplate><text>VLDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&FP registers to be transferred (field "D:Vd")"><dreglist></a></asmtemplate>
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</encoding>
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<encoding name="VLDM_A1" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 && U == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="ldmstm-mode" value="inc-after" />
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<docvar key="mnemonic" value="VLDM" />
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<docvar key="mnemonic-fpdatasize" value="VLDM-doubleprec" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>0</c>
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</box>
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<box hibit="23" width="1" name="U">
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<c>1</c>
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</box>
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<asmtemplate><text>VLDM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="Specifies base register writeback (field "W")">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&FP registers to be transferred (field "D:Vd")"><dreglist></a></asmtemplate>
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<asmtemplate><text>VLDMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="Specifies base register writeback (field "W")">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&FP registers to be transferred (field "D:Vd")"><dreglist></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VLDM/T1A1_A.txt" mylink="aarch32.instrs.VLDM.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '0' && U == '0' && W == '0' then SEE "Related encodings";
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if P == '1' && W == '0' then SEE "VLDR";
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if P == U && W == '1' then UNDEFINED;
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// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
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single_regs = FALSE; add = (U == '1'); wback = (W == '1');
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);
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regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8) DIV 2; // If UInt(imm8) is odd, see "FLDM*X".
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if n == 15 && (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;
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if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
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if imm8<0> == '1' && (d+regs) > 16 then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">regs == 0</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction operates as a <instruction>VLDM</instruction> with the same addressing mode but loads no registers.</cu_type_text>
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">regs > 16 || (d+regs) > 32</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VLDM/T2A2_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1">
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<c></c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="VLDMDB_A2" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 && U == 0 && W == 1">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="ldmstm-mode" value="dec-before" />
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<docvar key="mnemonic" value="VLDMDB" />
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<docvar key="mnemonic-fpdatasize" value="VLDMDB-singleprec" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="23" width="1" name="U">
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<c>0</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>1</c>
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</box>
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<asmtemplate><text>VLDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&FP registers to be transferred (field "Vd:D")"><sreglist></a></asmtemplate>
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</encoding>
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<encoding name="VLDM_A2" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 && U == 1">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="ldmstm-mode" value="inc-after" />
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<docvar key="mnemonic" value="VLDM" />
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<docvar key="mnemonic-fpdatasize" value="VLDM-singleprec" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>0</c>
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</box>
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<box hibit="23" width="1" name="U">
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<c>1</c>
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</box>
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<asmtemplate><text>VLDM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="Specifies base register writeback (field "W")">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&FP registers to be transferred (field "Vd:D")"><sreglist></a></asmtemplate>
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<asmtemplate><text>VLDMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="Specifies base register writeback (field "W")">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&FP registers to be transferred (field "Vd:D")"><sreglist></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VLDM/T2A2_A.txt" mylink="aarch32.instrs.VLDM.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '0' && U == '0' && W == '0' then SEE "Related encodings";
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if P == '1' && W == '0' then SEE "VLDR";
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if P == U && W == '1' then UNDEFINED;
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// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
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single_regs = TRUE; add = (U == '1'); wback = (W == '1'); d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32); regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8);
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if n == 15 && (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;
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if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A2" ps_block="Decode">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">regs == 0</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
<cu_type>
|
|
<cu_type_text>The instruction operates as a <instruction>VLDM</instruction> with the same addressing mode but loads no registers.</cu_type_text>
|
|
</cu_type>
|
|
</cu_case>
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">(d+regs) > 32</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
<cu_type>
|
|
<cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
|
|
</cu_type>
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</iclass>
|
|
<iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="doubleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VLDM/T1A1_A.txt" tworows="1">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" name="P" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="W" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" name="L" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size" settings="2">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="7" width="7" name="imm8<7:1>" usename="1">
|
|
<c colspan="7"></c>
|
|
</box>
|
|
<box hibit="0" name="imm8<0>" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VLDMDB_T1" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 && U == 0 && W == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="doubleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="ldmstm-mode" value="dec-before" />
|
|
<docvar key="mnemonic" value="VLDMDB" />
|
|
<docvar key="mnemonic-fpdatasize" value="VLDMDB-doubleprec" />
|
|
</docvars>
|
|
<box hibit="24" width="1" name="P">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="1" name="U">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" width="1" name="W">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VLDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>!, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&FP registers to be transferred (field "D:Vd")"><dreglist></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VLDM_T1" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 && U == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="fpdatasize" value="doubleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="ldmstm-mode" value="inc-after" />
|
|
<docvar key="mnemonic" value="VLDM" />
|
|
<docvar key="mnemonic-fpdatasize" value="VLDM-doubleprec" />
|
|
</docvars>
|
|
<box hibit="24" width="1" name="P">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="1" name="U">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VLDM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="Specifies base register writeback (field "W")">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&FP registers to be transferred (field "D:Vd")"><dreglist></a></asmtemplate>
|
|
<asmtemplate><text>VLDMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="Specifies base register writeback (field "W")">{!}</a><text>, </text><a link="sa_dreglist" hover="List of consecutively numbered 64-bit SIMD&FP registers to be transferred (field "D:Vd")"><dreglist></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VLDM/T1A1_A.txt" mylink="aarch32.instrs.VLDM.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '0' && U == '0' && W == '0' then SEE "Related encodings";
|
|
if P == '1' && W == '0' then SEE "VLDR";
|
|
if P == U && W == '1' then UNDEFINED;
|
|
// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
|
|
single_regs = FALSE; add = (U == '1'); wback = (W == '1');
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32);
|
|
regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8) DIV 2; // If UInt(imm8) is odd, see "FLDM*X".
|
|
if n == 15 && (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;
|
|
if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
|
|
if imm8<0> == '1' && (d+regs) > 16 then UNPREDICTABLE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<constrained_unpredictables encoding="T1" ps_block="Decode">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">regs == 0</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
<cu_type>
|
|
<cu_type_text>The instruction operates as a <instruction>VLDM</instruction> with the same addressing mode but loads no registers.</cu_type_text>
|
|
</cu_type>
|
|
</cu_case>
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">regs > 16 || (d+regs) > 32</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
<cu_type>
|
|
<cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
|
|
</cu_type>
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</iclass>
|
|
<iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="fpdatasize" value="singleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VLDM/T2A2_A.txt">
|
|
<box hibit="31" width="7" settings="7">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="24" name="P" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="23" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" name="W" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="20" name="L" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VLDMDB_T2" oneofinclass="2" oneof="8" label="Decrement Before" bitdiffs="P == 1 && U == 0 && W == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="fpdatasize" value="singleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="ldmstm-mode" value="dec-before" />
|
|
<docvar key="mnemonic" value="VLDMDB" />
|
|
<docvar key="mnemonic-fpdatasize" value="VLDMDB-singleprec" />
|
|
</docvars>
|
|
<box hibit="24" width="1" name="P">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="23" width="1" name="U">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="21" width="1" name="W">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VLDMDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>!, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&FP registers to be transferred (field "Vd:D")"><sreglist></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VLDM_T2" oneofinclass="2" oneof="8" label="Increment After" bitdiffs="P == 0 && U == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="fpdatasize" value="singleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="ldmstm-mode" value="inc-after" />
|
|
<docvar key="mnemonic" value="VLDM" />
|
|
<docvar key="mnemonic-fpdatasize" value="VLDM-singleprec" />
|
|
</docvars>
|
|
<box hibit="24" width="1" name="P">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" width="1" name="U">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VLDM</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="Specifies base register writeback (field "W")">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&FP registers to be transferred (field "Vd:D")"><sreglist></a></asmtemplate>
|
|
<asmtemplate><text>VLDMIA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>{</text><text>.</text><a link="sa_size" hover="An optional data size specifier"><size></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="Specifies base register writeback (field "W")">{!}</a><text>, </text><a link="sa_sreglist" hover="List of consecutively numbered 32-bit SIMD&FP registers to be transferred (field "Vd:D")"><sreglist></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VLDM/T2A2_A.txt" mylink="aarch32.instrs.VLDM.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '0' && U == '0' && W == '0' then SEE "Related encodings";
|
|
if P == '1' && W == '0' then SEE "VLDR";
|
|
if P == U && W == '1' then UNDEFINED;
|
|
// Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
|
|
single_regs = TRUE; add = (U == '1'); wback = (W == '1'); d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
|
imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32); regs = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8);
|
|
if n == 15 && (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;
|
|
if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<constrained_unpredictables encoding="T2" ps_block="Decode">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">regs == 0</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
<cu_type>
|
|
<cu_type_text>The instruction operates as a <instruction>VLDM</instruction> with the same addressing mode but loads no registers.</cu_type_text>
|
|
</cu_type>
|
|
</cu_case>
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">(d+regs) > 32</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
<cu_type>
|
|
<cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
|
|
</cu_type>
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="VLDM_A1, VLDM_A2, VLDM_T1, VLDM_T2" symboldefcount="1">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLDM_A1, VLDM_A2, VLDM_T1, VLDM_T2" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLDM_A1, VLDM_A2, VLDM_T1, VLDM_T2" symboldefcount="1">
|
|
<symbol link="sa_size"><size></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers being transferred.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLDM_A1, VLDM_A2, VLDM_T1, VLDM_T2" symboldefcount="1">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the general-purpose base register, encoded in the "Rn" field. If writeback is not specified, the PC can be used.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VLDM_A1, VLDM_A2, VLDM_T1, VLDM_T2" symboldefcount="1">
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<symbol link="sa_0d33">!</symbol>
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<account encodedin="W">
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<intro>
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<para>Specifies base register writeback. Encoded in the "W" field as 1 if present, otherwise 0.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VLDM_A2, VLDM_T2" symboldefcount="1">
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<symbol link="sa_sreglist"><sreglist></symbol>
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<account encodedin="">
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<intro>
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<para>Is the list of consecutively numbered 32-bit SIMD&FP registers to be transferred. The first register in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must contain at least one register.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VLDM_A1, VLDM_T1" symboldefcount="1">
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<symbol link="sa_dreglist"><dreglist></symbol>
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<account encodedin="">
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<intro>
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<para>Is the list of consecutively numbered 64-bit SIMD&FP registers to be transferred. The first register in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The list must contain at least one register, and must not contain more than 16 registers.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VLDM/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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<a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);
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address = if add then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-imm32;
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for r = 0 to regs-1
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if single_regs then
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<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d+r] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];
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address = address+4;
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else
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word1 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];
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word2 = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];
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address = address+8;
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// Combine the word-aligned words in the correct order for current endianness.
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<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_ASIMD" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_ASIMD</a>) then word1:word2 else word2:word1;
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if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = if add then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+imm32 else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-imm32;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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