425 lines
24 KiB
XML
425 lines
24 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VLD3_a" title="VLD3 (single 3-element structure to all lanes) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VLD3" />
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</docvars>
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<heading>VLD3 (single 3-element structure to all lanes)</heading>
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<desc>
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<brief>
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<para>Load single 3-element structure and replicate to all lanes of three registers</para>
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</brief>
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<authored>
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<para>Load single 3-element structure and replicate to all lanes of three registers loads one 3-element structure from memory into all lanes of three registers. For details of the addressing mode, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information, see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>, and particularly <xref linkend="CEGHGDDF">VLD3 (single 3-element structure to all lanes)</xref>.</para>
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</encodingnotes>
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<syntaxnotes>
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<para>For more information about the variants of this instruction, see <xref linkend="Cjaefebe">Advanced SIMD addressing mode</xref>.</para>
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<para>Alignment</para>
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<para>Standard alignment rules apply, see <xref linkend="CHDIDCCI">Alignment support</xref>.</para>
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</syntaxnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="3" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VLD3" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VLD3_a/T1A1_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="2" name="N" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="7" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="5" name="T" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="a" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VLD3_a_A1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VLD3" />
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</docvars>
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<box hibit="3" width="4" name="Rm">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32,UNDEFINED]"><size></a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&FP registers (field "T")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>]</text></asmtemplate>
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</encoding>
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<encoding name="VLD3_a_A1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VLD3" />
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</docvars>
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<box hibit="3" width="4" name="Rm">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32,UNDEFINED]"><size></a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&FP registers (field "T")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>]!</text></asmtemplate>
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</encoding>
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<encoding name="VLD3_a_A1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-offset" value="reg-offset" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VLD3" />
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</docvars>
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<box hibit="3" width="4" name="Rm">
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<c>N</c>
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<c>N</c>
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<c></c>
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<c>N</c>
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</box>
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<asmtemplate><text>VLD3</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32,UNDEFINED]"><size></a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&FP registers (field "T")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VLD3_a/T1A1_A.txt" mylink="aarch32.instrs.VLD3_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' || a == '1' then UNDEFINED;
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ebytes = 1 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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inc = if T == '0' then 1 else 2;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); d2 = d + inc; d3 = d2 + inc; n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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wback = (m != 15); register_index = (m != 15 && m != 13);
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if n == 15 || d3 > 31 then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">d3 > 31</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="3" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VLD3" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VLD3_a/T1A1_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="2" name="N" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="7" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="5" name="T" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="a" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VLD3_a_T1_nowb" oneofinclass="3" oneof="6" label="Offset" bitdiffs="Rm == 1111">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VLD3" />
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</docvars>
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<box hibit="3" width="4" name="Rm">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32,UNDEFINED]"><size></a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&FP registers (field "T")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>]</text></asmtemplate>
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</encoding>
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<encoding name="VLD3_a_T1_posti" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm == 1101">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VLD3" />
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</docvars>
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<box hibit="3" width="4" name="Rm">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32,UNDEFINED]"><size></a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&FP registers (field "T")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>]!</text></asmtemplate>
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</encoding>
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<encoding name="VLD3_a_T1_postr" oneofinclass="3" oneof="6" label="Post-indexed" bitdiffs="Rm != 11x1">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="address-offset" value="reg-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VLD3" />
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</docvars>
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<box hibit="3" width="4" name="Rm">
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<c>N</c>
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<c>N</c>
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<c></c>
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<c>N</c>
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</box>
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<asmtemplate><text>VLD3</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="Data size (field "size") [8,16,32,UNDEFINED]"><size></a><text> </text><a link="sa_list" hover="List containing the 64-bit names of three SIMD&FP registers (field "T")"><list></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>], </text><a link="sa_rm" hover="General-purpose index register containing an offset applied after the access (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VLD3_a/T1A1_A.txt" mylink="aarch32.instrs.VLD3_a.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if size == '11' || a == '1' then UNDEFINED;
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ebytes = 1 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
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inc = if T == '0' then 1 else 2;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); d2 = d + inc; d3 = d2 + inc; n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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wback = (m != 15); register_index = (m != 15 && m != 13);
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if n == 15 || d3 > 31 then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="T1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">d3 > 31</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>One or more of the SIMD and floating-point registers are <arm-defined-word>unknown</arm-defined-word>. If the instruction specifies writeback, the base register becomes <arm-defined-word>unknown</arm-defined-word>. This behavior does not affect any general-purpose registers.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VLD3_a_A1_nowb" symboldefcount="1">
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<symbol link="sa_c_1"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
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</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLD3_a_T1_nowb" symboldefcount="2">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
|
|
<symbol link="sa_size"><size></symbol>
|
|
<definition encodedin="size">
|
|
<intro>Is the data size, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">size</entry>
|
|
<entry class="symbol"><size></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="symbol">8</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="symbol">16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="symbol">32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="symbol">RESERVED</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
|
|
<symbol link="sa_list"><list></symbol>
|
|
<account encodedin="T">
|
|
<intro>
|
|
<para>Is a list containing the 64-bit names of three SIMD&FP registers.</para>
|
|
<para>The list must be one of:</para>
|
|
<list type="param">
|
|
<listitem>
|
|
<param><syntax>{ <Dd>[], <Dd+1>[], <Dd+2>[] }</syntax></param><content>Single-spaced registers, encoded in the "T" field as <binarynumber>0</binarynumber>.</content>
|
|
</listitem>
|
|
<listitem>
|
|
<param><syntax>{ <Dd>[], <Dd+2>[], <Dd+4>[] }</syntax></param><content>Double-spaced registers, encoded in the "T" field as <binarynumber>1</binarynumber>.</content>
|
|
</listitem>
|
|
</list>
|
|
<para>The register <syntax><Dd></syntax> is encoded in the "D:Vd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLD3_a_A1_nowb, VLD3_a_T1_nowb" symboldefcount="1">
|
|
<symbol link="sa_rn"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the general-purpose base register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VLD3_a_A1_postr, VLD3_a_T1_postr" symboldefcount="1">
|
|
<symbol link="sa_rm"><Rm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the general-purpose index register containing an offset applied after the access, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VLD3_a/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
|
|
address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
|
|
constant integer esize = ebytes * 8;
|
|
bits(esize) element1 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address, ebytes];
|
|
bits(esize) element2 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+ebytes,ebytes];
|
|
bits(esize) element3 = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address+2*ebytes,ebytes];
|
|
|
|
<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element1, 64 DIV esize);
|
|
<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d2] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element2, 64 DIV esize);
|
|
<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d3] = <a link="impl-shared.Replicate.2" file="shared_pseudocode.xml" hover="function: bits(M*N) Replicate(bits(M) x, integer N)">Replicate</a>(element3, 64 DIV esize);
|
|
if wback then
|
|
if register_index then
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m];
|
|
else
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + 3*ebytes;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|