243 lines
12 KiB
XML
243 lines
12 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VJCVT" title="VJCVT -- AArch32" type="instruction">
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<docvars>
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<docvar key="convert-type" value="double-to-single" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VJCVT" />
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</docvars>
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<heading>VJCVT</heading>
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<desc>
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<brief>
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<para>Javascript Convert to signed fixed-point, rounding toward Zero</para>
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</brief>
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<authored>
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<para>Javascript Convert to signed fixed-point, rounding toward Zero. This instruction converts the double-precision floating-point value in the SIMD&FP source register to a 32-bit signed integer using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register. If the result is too large to be accommodated as a signed 32-bit integer, then the result is the integer modulo 2<sup>32</sup>, as held in a 32-bit signed integer.</para>
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<para>This instruction can generate a floating-point exception. Depending on the settings in <xref linkend="AArch32.fpscr">FPSCR</xref>, the exception results in either a flag being set or a synchronous exception being generated. For more information, see <xref linkend="CFIHBHHD">Floating-point exceptions and exception traps</xref>.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="convert-type" value="double-to-single" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VJCVT" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.3" feature="FEAT_JSCVT" />
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</arch_variants>
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<regdiagram form="32" psname="aarch32/instrs/VJCVT/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="19" name="o1" settings="1">
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<c>1</c>
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</box>
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<box hibit="18" width="3" name="opc2" settings="3">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="7" name="o3" settings="1">
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<c>1</c>
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</box>
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<box hibit="6" settings="1">
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<c>1</c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VJCVT_A1" oneofinclass="1" oneof="2" label="A1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="convert-type" value="double-to-single" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VJCVT" />
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</docvars>
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<asmtemplate><text>VJCVT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.S32.F64 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_dm" hover="64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VJCVT/A1_A.txt" mylink="aarch32.instrs.VJCVT.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFJCVTZSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFJCVTZSExt()">HaveFJCVTZSExt</a>() then UNDEFINED;
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if cond != '1110' then UNPREDICTABLE;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="convert-type" value="double-to-single" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VJCVT" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.3" feature="FEAT_JSCVT" />
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</arch_variants>
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<regdiagram form="16x2" psname="aarch32/instrs/VJCVT/T1_A.txt">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="19" name="o1" settings="1">
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<c>1</c>
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</box>
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<box hibit="18" width="3" name="opc2" settings="3">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="7" name="o3" settings="1">
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<c>1</c>
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</box>
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<box hibit="6" settings="1">
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<c>1</c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VJCVT_T1" oneofinclass="1" oneof="2" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="convert-type" value="double-to-single" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VJCVT" />
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</docvars>
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<asmtemplate><text>VJCVT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.S32.F64 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_dm" hover="64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VJCVT/T1_A.txt" mylink="aarch32.instrs.VJCVT.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFJCVTZSExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFJCVTZSExt()">HaveFJCVTZSExt</a>() then UNDEFINED;
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if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VJCVT_A1, VJCVT_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VJCVT_A1, VJCVT_T1" symboldefcount="1">
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<symbol link="sa_sd"><Sd></symbol>
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<account encodedin="Vd:D">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VJCVT_A1, VJCVT_T1" symboldefcount="1">
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<symbol link="sa_dm"><Dm></symbol>
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<account encodedin="M:Vm">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VJCVT/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">EncodingSpecificOperations();
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<a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);
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bits(64) fltval = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m];
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bits(32) intval;
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bit Z;
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(intval, Z) = <a link="impl-shared.FPToFixedJS.4" file="shared_pseudocode.xml" hover="function: (bits(N), bit) FPToFixedJS(bits(M) op, FPCRType fpcr, boolean Is64, integer N)">FPToFixedJS</a>(fltval, FPSCR[], FALSE, 32);
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FPSCR<31:28> = '0':Z:'00';
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<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = intval;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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