387 lines
21 KiB
XML
387 lines
21 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VHSUB" title="VHSUB -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VHSUB" />
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</docvars>
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<heading>VHSUB</heading>
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<desc>
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<brief>
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<para>Vector Halving Subtract</para>
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</brief>
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<authored>
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<para>Vector Halving Subtract subtracts the elements of the second operand from the corresponding elements of the first operand, shifts each result right one bit, and places the final results in the destination vector. The results of the halving operations are truncated. There is no rounding version.</para>
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<para>The operand and result elements are all the same type, and can be any one of:</para>
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<list type="unordered">
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<listitem><content>8-bit, 16-bit, or 32-bit signed integers.</content></listitem>
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<listitem><content>8-bit, 16-bit, or 32-bit unsigned integers.</content></listitem>
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</list>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VHSUB" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VHADD/T1A1_A.txt" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="23" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" name="op" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="8" settings="1">
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<c>0</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="o1" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VHSUB_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VHSUB" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VHSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field "U:size")"><dt></a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<encoding name="VHSUB_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VHSUB" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VHSUB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field "U:size")"><dt></a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&FP source register (field "N:Vn")"><Qn></a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&FP source register (field "M:Vm")"><Qm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VHADD/T1A1_A.txt" mylink="aarch32.instrs.VHADD.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
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if size == '11' then UNDEFINED;
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add = (op == '0'); unsigned = (U == '1');
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esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size); elements = 64 DIV esize;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VHSUB" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VHADD/T1A1_A.txt" tworows="1">
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<box hibit="31" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="28" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="9" name="op" usename="1" settings="1">
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<c>1</c>
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</box>
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<box hibit="8" settings="1">
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<c>0</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="o1" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VHSUB_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VHSUB" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VHSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field "U:size")"><dt></a><text> </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><text>}</text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<encoding name="VHSUB_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VHSUB" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VHSUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of operands (field "U:size")"><dt></a><text> </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><text>}</text><a link="sa_qn" hover="First 128-bit SIMD&FP source register (field "N:Vn")"><Qn></a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&FP source register (field "M:Vm")"><Qm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VHADD/T1A1_A.txt" mylink="aarch32.instrs.VHADD.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
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if size == '11' then UNDEFINED;
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add = (op == '0'); unsigned = (U == '1');
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esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size); elements = 64 DIV esize;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VHSUB_A1_Q" symboldefcount="1">
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<symbol link="sa_c_1"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VHSUB_T1_Q" symboldefcount="2">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VHSUB_A1_Q, VHSUB_T1_Q" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VHSUB_A1_Q, VHSUB_T1_Q" symboldefcount="1">
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<symbol link="sa_dt"><dt></symbol>
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<definition encodedin="U:size">
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<intro>Is the data type for the elements of the operands, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">U</entry>
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<entry class="bitfield">size</entry>
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<entry class="symbol"><dt></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">00</entry>
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<entry class="symbol">S8</entry>
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</row>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">01</entry>
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<entry class="symbol">S16</entry>
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</row>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="bitfield">10</entry>
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<entry class="symbol">S32</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="bitfield">00</entry>
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<entry class="symbol">U8</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="bitfield">01</entry>
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<entry class="symbol">U16</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="bitfield">10</entry>
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<entry class="symbol">U32</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="VHSUB_A1_Q, VHSUB_T1_Q" symboldefcount="1">
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<symbol link="sa_qd"><Qd></symbol>
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<account encodedin="D:Vd">
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<intro>
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<para>Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VHSUB_A1_Q, VHSUB_T1_Q" symboldefcount="1">
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<symbol link="sa_qn"><Qn></symbol>
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<account encodedin="N:Vn">
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<intro>
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<para>Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VHSUB_A1_Q, VHSUB_T1_Q" symboldefcount="1">
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<symbol link="sa_qm"><Qm></symbol>
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<account encodedin="M:Vm">
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<intro>
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<para>Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VHSUB_A1_D, VHSUB_T1_D" symboldefcount="1">
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<symbol link="sa_dd"><Dd></symbol>
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<account encodedin="D:Vd">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
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</intro>
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</account>
|
|
</explanation>
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<explanation enclist="VHSUB_A1_D, VHSUB_T1_D" symboldefcount="1">
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<symbol link="sa_dn"><Dn></symbol>
|
|
<account encodedin="N:Vn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.</para>
|
|
</intro>
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|
</account>
|
|
</explanation>
|
|
<explanation enclist="VHSUB_A1_D, VHSUB_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dm"><Dm></symbol>
|
|
<account encodedin="M:Vm">
|
|
<intro>
|
|
<para>Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
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|
<ps name="aarch32/instrs/VHADD/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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|
EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
|
|
for r = 0 to regs-1
|
|
for e = 0 to elements-1
|
|
op1 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize], unsigned);
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|
op2 = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], unsigned);
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|
result = (if add then op1+op2 else op1-op2) >> 1;
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result<esize-1:0>;</pstext>
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|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|