344 lines
18 KiB
XML
344 lines
18 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VFMAL" title="VFMAL (vector) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VFMAL" />
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</docvars>
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<heading>VFMAL (vector)</heading>
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<desc>
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<brief>
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<para>Vector Floating-point Multiply-Add Long to accumulator (vector)</para>
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</brief>
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<authored>
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<para>Vector Floating-point Multiply-Add Long to accumulator (vector). This instruction multiplies corresponding values in the vectors in the two source SIMD&FP registers, and accumulates the product to the corresponding vector element of the destination SIMD&FP register. The instruction does not round the result of the multiply before the accumulation.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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<para>In Armv8.2 and Armv8.3, this is an <arm-defined-word>optional</arm-defined-word> instruction. From Armv8.4 it is mandatory for all implementations to support it.</para>
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<note>
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<para><xref linkend="AArch32.id_isar6">ID_ISAR6</xref>.FHM indicates whether this instruction is supported.</para>
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</note>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMAL" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FHM" />
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</arch_variants>
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<regdiagram form="32" psname="aarch32/instrs/VFMAL/A1_A.txt" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" name="S" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="op2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" settings="1">
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<c>1</c>
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</box>
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<box hibit="10" name="op3" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" settings="1">
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<c>0</c>
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</box>
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<box hibit="8" name="op4" settings="1">
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<c>0</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="U" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VFMAL_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMAL" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VFMAL_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMAL" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VFMAL/A1_A.txt" mylink="aarch32.instrs.VFMAL.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;
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if Q == '1' && Vd<0> == '1' then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
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integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);
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integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
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integer esize = 32;
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integer regs = if Q=='1' then 2 else 1;
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integer datasize = if Q=='1' then 64 else 32;
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boolean sub_op = S=='1';</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VFMAL" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FHM" />
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</arch_variants>
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<regdiagram form="16x2" psname="aarch32/instrs/VFMAL/T1_A.txt" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" name="S" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="op2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" settings="1">
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<c>1</c>
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</box>
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<box hibit="10" name="op3" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" settings="1">
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<c>0</c>
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</box>
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<box hibit="8" name="op4" settings="1">
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<c>0</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="U" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VFMAL_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VFMAL" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VFMAL_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VFMAL" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VFMAL</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VFMAL/T1_A.txt" mylink="aarch32.instrs.VFMAL.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
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if !<a link="impl-shared.HaveFP16MulNoRoundingToFP32Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16MulNoRoundingToFP32Ext()">HaveFP16MulNoRoundingToFP32Ext</a>() then UNDEFINED;
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if Q == '1' && Vd<0> == '1' then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
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integer n = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N);
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integer m = if Q == '1' then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
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integer esize = 32;
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integer regs = if Q=='1' then 2 else 1;
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integer datasize = if Q=='1' then 64 else 32;
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boolean sub_op = S=='1';</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VFMAL_A1_Q, VFMAL_T1_Q" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VFMAL_A1_Q, VFMAL_T1_Q" symboldefcount="1">
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<symbol link="sa_qd"><Qd></symbol>
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<account encodedin="D:Vd">
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<intro>
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<para>Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VFMAL_A1_Q, VFMAL_T1_Q" symboldefcount="1">
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<symbol link="sa_dn"><Dn></symbol>
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<account encodedin="N:Vn">
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<intro>
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<para>Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VFMAL_A1_Q, VFMAL_T1_Q" symboldefcount="1">
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<symbol link="sa_dm"><Dm></symbol>
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<account encodedin="M:Vm">
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<intro>
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<para>Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VFMAL_A1_D, VFMAL_T1_D" symboldefcount="1">
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<symbol link="sa_dd"><Dd></symbol>
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<account encodedin="D:Vd">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VFMAL_A1_D, VFMAL_T1_D" symboldefcount="1">
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<symbol link="sa_sn"><Sn></symbol>
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<account encodedin="Vn:N">
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<intro>
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<para>Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VFMAL_A1_D, VFMAL_T1_D" symboldefcount="1">
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<symbol link="sa_sm"><Sm></symbol>
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<account encodedin="Vm:M">
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<intro>
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<para>Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VFMAL/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
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bits(datasize) operand1 ;
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bits(datasize) operand2 ;
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bits(64) operand3;
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bits(64) result;
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bits(esize DIV 2) element1;
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bits(esize DIV 2) element2;
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if Q=='0' then
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operand1 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]<datasize-1:0>;
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operand2 = <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]<datasize-1:0>;
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else
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operand1 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n]<datasize-1:0>;
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operand2 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m]<datasize-1:0>;
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for r = 0 to regs-1
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operand3 = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r];
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for e = 0 to 1
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element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2*r+e, esize DIV 2];
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element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2*r+e, esize DIV 2];
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if sub_op then element1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(element1);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.FPMulAddH.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAddH(bits(N) addend, bits(N DIV 2) op1, bits(N DIV 2) op2, FPCRType fpcr)">FPMulAddH</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize], element1, element2,
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<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());
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<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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