294 lines
15 KiB
XML
294 lines
15 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VFMA_bf" title="VFMAB, VFMAT (BFloat16, vector) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VFMA" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<heading>VFMAB, VFMAT (BFloat16, vector)</heading>
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<desc>
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<brief>
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<para>BFloat16 floating-point widening multiply-add long (vector)</para>
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</brief>
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<authored>
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<para>The Bfloat16 floating-point widening multiply-add long instruction widens the even-numbered (bottom) or odd-numbered (top) 16-bit elements in the first and second source vectors from Bfloat16 to single-precision format. The instruction then multiplies and adds these values to the overlapping single-precision elements of the destination vector.</para>
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<para>Unlike other BFloat16 multiplication instructions, this performs a fused multiply-add, without intermediate rounding that uses the Round to Nearest rounding mode and can generate a floating-point exception that causes cumulative exception bits in the <xref linkend="AArch32.fpscr">FPSCR</xref> to be set.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMA" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
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</arch_variants>
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<regdiagram form="32" psname="aarch32/instrs/VFMA_bf/A1_A.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" width="2" name="op1" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="op2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" settings="1">
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<c>1</c>
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</box>
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<box hibit="10" name="op3" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" settings="1">
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<c>0</c>
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</box>
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<box hibit="8" name="op4" settings="1">
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<c>0</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="U" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VFMA_bf_A1_Q" oneofinclass="1" oneof="2" label="A1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMA" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<asmtemplate><text>VFMA</text><a link="sa_bt" hover="Bottom or top element specifier (field "Q")"><bt></a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&FP source register (field "N:Vn")"><Qn></a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&FP source register (field "M:Vm")"><Qm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VFMA_bf/A1_A.txt" mylink="aarch32.instrs.VFMA_bf.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;
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if Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1' then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
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integer elements = 128 DIV 32;
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integer sel = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VFMA" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<arch_variants>
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<arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
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</arch_variants>
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<regdiagram form="16x2" psname="aarch32/instrs/VFMA_bf/T1_A.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" width="2" name="op1" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="op2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" settings="1">
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<c>1</c>
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</box>
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<box hibit="10" name="op3" settings="1">
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<c>0</c>
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</box>
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<box hibit="9" settings="1">
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<c>0</c>
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</box>
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<box hibit="8" name="op4" settings="1">
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<c>0</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="U" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VFMA_bf_T1_Q" oneofinclass="1" oneof="2" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VFMA" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<asmtemplate><text>VFMA</text><a link="sa_bt" hover="Bottom or top element specifier (field "Q")"><bt></a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&FP source register (field "N:Vn")"><Qn></a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&FP source register (field "M:Vm")"><Qm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VFMA_bf/T1_A.txt" mylink="aarch32.instrs.VFMA_bf.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
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if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;
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if Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1' then UNDEFINED;
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integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
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integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);
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integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
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integer elements = 128 DIV 32;
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integer sel = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
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<symbol link="sa_bt"><bt></symbol>
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<definition encodedin="Q">
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<intro>Is the bottom or top element specifier, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">Q</entry>
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<entry class="symbol"><bt></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">B</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">T</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
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<symbol link="sa_qd"><Qd></symbol>
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<account encodedin="D:Vd">
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<intro>
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<para>Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
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<symbol link="sa_qn"><Qn></symbol>
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<account encodedin="N:Vn">
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<intro>
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<para>Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VFMA_bf_A1_Q, VFMA_bf_T1_Q" symboldefcount="1">
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<symbol link="sa_qm"><Qm></symbol>
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<account encodedin="M:Vm">
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<intro>
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<para>Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VFMA_bf/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
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bits(128) operand1 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[n>>1];
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bits(128) operand2 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[m>>1];
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bits(128) operand3 = <a link="impl-aarch32.Q.read.1" file="shared_pseudocode.xml" hover="accessor: bits(128) Q[integer n]">Q</a>[d>>1];
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bits(128) result;
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for e = 0 to elements-1
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bits(32) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + sel, 16] : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);
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bits(32) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + sel, 16] : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16);
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bits(32) addend = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 32];
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(addend, element1, element2,
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<a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());
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<a link="impl-aarch32.Q.write.1" file="shared_pseudocode.xml" hover="accessor: Q[integer n] = bits(128) value">Q</a>[d>>1] = result;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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