698 lines
40 KiB
XML
698 lines
40 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VFMA" title="VFMA -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VFMA" />
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</docvars>
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<heading>VFMA</heading>
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<desc>
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<brief>
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<para>Vector Fused Multiply Accumulate</para>
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</brief>
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<authored>
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<para>Vector Fused Multiply Accumulate multiplies corresponding elements of two vectors, and accumulates the results into the elements of the destination vector. The instruction does not round the result of the multiply before the accumulation.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="4">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt> and </txt>
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<a href="#iclass_a2">A2</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t2">T2</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMA" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VFMA/A1_A.txt" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="op" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" name="sz" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="opc" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="o1" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VFMA_A1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMA" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VFMA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field "sz") [F16,F32]"><dt></a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<encoding name="VFMA_A1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMA" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VFMA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field "sz") [F16,F32]"><dt></a><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&FP source register (field "N:Vn")"><Qn></a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&FP source register (field "M:Vm")"><Qm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VFMA/A1_A.txt" mylink="aarch32.instrs.VFMA.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
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if sz == '1' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
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advsimd = TRUE; op1_neg = (op == '1');
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integer esize;
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integer elements;
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case sz of
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when '0' esize = 32; elements = 2;
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when '1' esize = 16; elements = 4;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
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regs = if Q == '0' then 1 else 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="A2" oneof="4" id="iclass_a2" no_encodings="3" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMA" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VFMA/A2_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" name="o0" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" name="o1" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="7" name="N" usename="1">
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<c></c>
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</box>
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<box hibit="6" name="op" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VFMA_A2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="fpdatasize" value="halfprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMA" />
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<docvar key="mnemonic-fpdatasize" value="VFMA-halfprec" />
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</docvars>
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<arch_variants>
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<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
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</arch_variants>
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<box hibit="9" width="2" name="size">
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<c>0</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VFMA_A2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="fpdatasize" value="singleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMA" />
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<docvar key="mnemonic-fpdatasize" value="VFMA-singleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>0</c>
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</box>
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<asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VFMA_A2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="fpdatasize" value="doubleprec" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VFMA" />
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<docvar key="mnemonic-fpdatasize" value="VFMA-doubleprec" />
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</docvars>
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<box hibit="9" width="2" name="size">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VFMA/A2_A.txt" mylink="aarch32.instrs.VFMA.A2_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
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if size == '00' || (size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
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if size == '01' && cond != '1110' then UNPREDICTABLE;
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advsimd = FALSE; op1_neg = (op == '1');
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integer esize;
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integer d;
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integer n;
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integer m;
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case size of
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when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
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when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
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when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A2" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">size == '01' && cond != '1110'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type>
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<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
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</cu_type>
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<cu_type>
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<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
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</cu_type>
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<arch_variants>
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<arch_variant name="ARMv8.2-A" />
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</arch_variants>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VFMA" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VFMA/T1_A.txt" tworows="1">
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<box hibit="31" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="28" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="op" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="20" name="sz" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Vn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="opc" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="7" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="6" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" name="o1" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Vm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VFMA_T1_D" oneofinclass="2" oneof="10" label="64-bit SIMD vector" bitdiffs="Q == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VFMA" />
|
|
<docvar key="simdvectorsize" value="double" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field "sz") [F16,F32]"><dt></a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VFMA_T1_Q" oneofinclass="2" oneof="10" label="128-bit SIMD vector" bitdiffs="Q == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VFMA" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt" hover="Data type for elements of vectors (field "sz") [F16,F32]"><dt></a><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&FP source register (field "N:Vn")"><Qn></a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&FP source register (field "M:Vm")"><Qm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VFMA/T1_A.txt" mylink="aarch32.instrs.VFMA.T1_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
|
|
if sz == '1' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
|
|
if sz == '1' && <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
|
|
advsimd = TRUE; op1_neg = (op == '1');
|
|
integer esize;
|
|
integer elements;
|
|
case sz of
|
|
when '0' esize = 32; elements = 2;
|
|
when '1' esize = 16; elements = 4;
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
|
|
regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<constrained_unpredictables encoding="T1" ps_block="Decode">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">sz == '1' && InITBlock()</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
|
|
</cu_type>
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
|
|
</cu_type>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</iclass>
|
|
<iclass name="T2" oneof="4" id="iclass_t2" no_encodings="3" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VFMA" />
|
|
</docvars>
|
|
<iclassintro count="3"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VFMA/T2_A.txt" tworows="1">
|
|
<box hibit="31" width="8" settings="8">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="23" name="o0" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="2" name="o1" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Vn" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="9" width="2" name="size" usename="1">
|
|
<c colspan="2"></c>
|
|
</box>
|
|
<box hibit="7" name="N" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="6" name="op" usename="1" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="5" name="M" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Vm" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VFMA_T2_H" oneofinclass="3" oneof="10" label="Half-precision scalar" bitdiffs="size == 01">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="fpdatasize" value="halfprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VFMA" />
|
|
<docvar key="mnemonic-fpdatasize" value="VFMA-halfprec" />
|
|
</docvars>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2" feature="FEAT_FP16" />
|
|
</arch_variants>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>0</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F16 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VFMA_T2_S" oneofinclass="3" oneof="10" label="Single-precision scalar" bitdiffs="size == 10">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="fpdatasize" value="singleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VFMA" />
|
|
<docvar key="mnemonic-fpdatasize" value="VFMA-singleprec" />
|
|
</docvars>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F32 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_sn" hover="First 32-bit SIMD&FP source register (field "Vn:N")"><Sn></a><text>, </text><a link="sa_sm" hover="Second 32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VFMA_T2_D" oneofinclass="3" oneof="10" label="Double-precision scalar" bitdiffs="size == 11">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="fpdatasize" value="doubleprec" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VFMA" />
|
|
<docvar key="mnemonic-fpdatasize" value="VFMA-doubleprec" />
|
|
</docvars>
|
|
<box hibit="9" width="2" name="size">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VFMA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F64 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&FP source register (field "N:Vn")"><Dn></a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VFMA/T2_A.txt" mylink="aarch32.instrs.VFMA.T2_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
|
|
if size == '00' || (size == '01' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>()) then UNDEFINED;
|
|
if size == '01' && <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
|
|
advsimd = FALSE; op1_neg = (op == '1');
|
|
integer esize;
|
|
integer d;
|
|
integer n;
|
|
integer m;
|
|
case size of
|
|
when '01' esize = 16; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
|
|
when '10' esize = 32; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vn:N); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);
|
|
when '11' esize = 64; d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<constrained_unpredictables encoding="T2" ps_block="Decode">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">size == '01' && InITBlock()</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes as if it passes the Condition code check.</cu_type_text>
|
|
</cu_type>
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes as NOP. This means it behaves as if it fails the Condition code check.</cu_type_text>
|
|
</cu_type>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="VFMA_A1_Q" symboldefcount="1">
|
|
<symbol link="sa_c_1"><c></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VFMA_A2_H, VFMA_T1_Q, VFMA_T2_H" symboldefcount="2">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>For encoding A2, T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VFMA_A1_Q, VFMA_A2_H, VFMA_T1_Q, VFMA_T2_H" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VFMA_A1_Q, VFMA_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_dt"><dt></symbol>
|
|
<definition encodedin="sz">
|
|
<intro>Is the data type for the elements of the vectors, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">sz</entry>
|
|
<entry class="symbol"><dt></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</explanation>
|
|
<explanation enclist="VFMA_A1_Q, VFMA_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_qd"><Qd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VFMA_A1_Q, VFMA_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_qn"><Qn></symbol>
|
|
<account encodedin="N:Vn">
|
|
<intro>
|
|
<para>Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VFMA_A1_Q, VFMA_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_qm"><Qm></symbol>
|
|
<account encodedin="M:Vm">
|
|
<intro>
|
|
<para>Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VFMA_A1_D, VFMA_A2_D, VFMA_T1_D, VFMA_T2_D" symboldefcount="1">
|
|
<symbol link="sa_dd"><Dd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VFMA_A1_D, VFMA_A2_D, VFMA_T1_D, VFMA_T2_D" symboldefcount="1">
|
|
<symbol link="sa_dn"><Dn></symbol>
|
|
<account encodedin="N:Vn">
|
|
<intro>
|
|
<para>Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VFMA_A1_D, VFMA_A2_D, VFMA_T1_D, VFMA_T2_D" symboldefcount="1">
|
|
<symbol link="sa_dm"><Dm></symbol>
|
|
<account encodedin="M:Vm">
|
|
<intro>
|
|
<para>Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VFMA_A2_H, VFMA_T2_H" symboldefcount="1">
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<symbol link="sa_sd"><Sd></symbol>
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<account encodedin="Vd:D">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VFMA_A2_H, VFMA_T2_H" symboldefcount="1">
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<symbol link="sa_sn"><Sn></symbol>
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<account encodedin="Vn:N">
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<intro>
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<para>Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VFMA_A2_H, VFMA_T2_H" symboldefcount="1">
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<symbol link="sa_sm"><Sm></symbol>
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<account encodedin="Vm:M">
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<intro>
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<para>Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VFMA/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDOrVFPEnabled.2" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDOrVFPEnabled(boolean include_fpexc_check, boolean advsimd)">CheckAdvSIMDOrVFPEnabled</a>(TRUE, advsimd);
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if advsimd then // Advanced SIMD instruction
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for r = 0 to regs-1
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for e = 0 to elements-1
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bits(esize) op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n+r],e,esize];
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if op1_neg then op1 = <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(op1);
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r],e,esize],
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op1, <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize], <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>());
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else // VFP instruction
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case esize of
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when 16
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op16 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]<15:0>) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]<15:0>;
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<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(16) : <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d]<15:0>, op16, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m]<15:0>, FPSCR[]);
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when 32
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op32 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n]) else <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[n];
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<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[d], op32, <a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[]);
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when 64
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op64 = if op1_neg then <a link="impl-shared.FPNeg.1" file="shared_pseudocode.xml" hover="function: bits(N) FPNeg(bits(N) op)">FPNeg</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n]) else <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[n];
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<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPMulAdd.4" file="shared_pseudocode.xml" hover="function: bits(N) FPMulAdd(bits(N) addend, bits(N) op1, bits(N) op2, FPCRType fpcr)">FPMulAdd</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d], op64, <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[]);</pstext>
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</ps>
|
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</ps_section>
|
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</instructionsection>
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