303 lines
15 KiB
XML
303 lines
15 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VDUP_r" title="VDUP (general-purpose register) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VDUP" />
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</docvars>
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<heading>VDUP (general-purpose register)</heading>
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<desc>
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<brief>
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<para>Duplicate general-purpose register to vector</para>
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</brief>
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<authored>
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<para>Duplicate general-purpose register to vector duplicates an element from a general-purpose register into every element of the destination vector.</para>
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<para>The destination vector elements can be 8-bit, 16-bit, or 32-bit fields. The source element is the least significant 8, 16, or 32 bits of the general-purpose register. There is no distinction between data types.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VDUP" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VDUP_r/T1A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="B" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="7" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="6" settings="1">
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<c>0</c>
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</box>
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<box hibit="5" name="E" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="2" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="1" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="0" settings="1">
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<c>(0)</c>
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</box>
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</regdiagram>
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<encoding name="VDUP_r_A1" oneofinclass="1" oneof="2" label="A1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VDUP" />
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</docvars>
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<asmtemplate comment="Encoded as Q = 1"><text>VDUP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="The data size for elements of destination vector"><size></a><text> </text><a link="sa_qd" hover="The destination vector for a quadword operation"><Qd></a><text>, </text><a link="sa_rt" hover="The Arm source register"><Rt></a></asmtemplate>
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<asmtemplate comment="Encoded as Q = 0"><text>VDUP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="The data size for elements of destination vector"><size></a><text> </text><a link="sa_dd" hover="The destination vector for a doubleword operation"><Dd></a><text>, </text><a link="sa_rt" hover="The Arm source register"><Rt></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VDUP_r/T1A1_A.txt" mylink="aarch32.instrs.VDUP_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Q == '1' && Vd<0> == '1' then UNDEFINED;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); regs = if Q == '0' then 1 else 2;
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integer esize;
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integer elements;
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case B:E of
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when '00' esize = 32; elements = 2;
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when '01' esize = 16; elements = 4;
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when '10' esize = 8; elements = 8;
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when '11' UNDEFINED;
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if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VDUP" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VDUP_r/T1A1_A.txt">
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<box hibit="31" width="8" settings="8">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="B" usename="1">
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<c></c>
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</box>
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<box hibit="21" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="7" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="6" settings="1">
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<c>0</c>
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</box>
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<box hibit="5" name="E" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="2" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="1" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="0" settings="1">
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<c>(0)</c>
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</box>
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</regdiagram>
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<encoding name="VDUP_r_T1" oneofinclass="1" oneof="2" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VDUP" />
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</docvars>
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<asmtemplate comment="Encoded as Q = 1"><text>VDUP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="The data size for elements of destination vector"><size></a><text> </text><a link="sa_qd" hover="The destination vector for a quadword operation"><Qd></a><text>, </text><a link="sa_rt" hover="The Arm source register"><Rt></a></asmtemplate>
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<asmtemplate comment="Encoded as Q = 0"><text>VDUP</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_size" hover="The data size for elements of destination vector"><size></a><text> </text><a link="sa_dd" hover="The destination vector for a doubleword operation"><Dd></a><text>, </text><a link="sa_rt" hover="The Arm source register"><Rt></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VDUP_r/T1A1_A.txt" mylink="aarch32.instrs.VDUP_r.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Q == '1' && Vd<0> == '1' then UNDEFINED;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); regs = if Q == '0' then 1 else 2;
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integer esize;
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integer elements;
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case B:E of
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when '00' esize = 32; elements = 2;
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when '01' esize = 16; elements = 4;
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when '10' esize = 8; elements = 8;
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when '11' UNDEFINED;
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if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Arm strongly recommends that any <instruction>VDUP</instruction> instruction is unconditional, see <xref linkend="BABGABFG">Conditional execution</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
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<symbol link="sa_size"><size></symbol>
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<account encodedin="">
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<intro>
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<para>The data size for the elements of the destination vector. It must be one of:</para>
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<list type="param">
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<listitem>
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<param>8</param><content>Encoded as [b, e] = <binarynumber>0b10</binarynumber>.</content>
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</listitem>
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<listitem>
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<param>16</param><content>Encoded as [b, e] = <binarynumber>0b01</binarynumber>.</content>
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</listitem>
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<listitem>
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<param>32</param><content>Encoded as [b, e] = <binarynumber>0b00</binarynumber>.</content>
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</listitem>
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</list>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
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<symbol link="sa_qd"><Qd></symbol>
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<account encodedin="">
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<intro>
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<para>The destination vector for a quadword operation.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
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<symbol link="sa_dd"><Dd></symbol>
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<account encodedin="">
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<intro>
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<para>The destination vector for a doubleword operation.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VDUP_r_A1, VDUP_r_T1" symboldefcount="1">
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<symbol link="sa_rt"><Rt></symbol>
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<account encodedin="">
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<intro>
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<para>The Arm source register.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VDUP_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
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scalar = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]<esize-1:0>;
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for r = 0 to regs-1
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for e = 0 to elements-1
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<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = scalar;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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