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slonik/specs/vdot.xml

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<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
<instructionsection id="VDOT" title="VDOT (vector) -- AArch32" type="instruction">
<docvars>
<docvar key="instr-class" value="fpsimd" />
<docvar key="mnemonic" value="VDOT" />
</docvars>
<heading>VDOT (vector)</heading>
<desc>
<brief>
<para>BFloat16 floating-point (BF16) dot product (vector)</para>
</brief>
<authored>
<para>BFloat16 floating-point (BF16) dot product (vector). This instruction delimits the source vectors into pairs of 16-bit BF16 elements. Within each pair, the elements in the first source vector are multiplied by the corresponding elements in the second source vector. The resulting single-precision products are then summed and added destructively to the single-precision element in the destination vector which aligns with the pair of BF16 values in the first source vector. The instruction does not update the <xref linkend="AArch32.fpscr">FPSCR</xref> exception status.</para>
</authored>
</desc>
<alias_list howmany="0"></alias_list>
<classes>
<classesintro count="2">
<txt>It has encodings from the following instruction sets:</txt>
<txt> A32 (</txt>
<a href="#iclass_a1">A1</a>
<txt>)</txt>
<txt> and </txt>
<txt> T32 (</txt>
<a href="#iclass_t1">T1</a>
<txt>)</txt>
<txt>.</txt>
</classesintro>
<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
<docvars>
<docvar key="armarmheading" value="A1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="A32" />
<docvar key="mnemonic" value="VDOT" />
</docvars>
<iclassintro count="2"></iclassintro>
<arch_variants>
<arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
</arch_variants>
<regdiagram form="32" psname="aarch32/instrs/VDOT_bf16/A1_A.txt">
<box hibit="31" width="7" settings="7">
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="24" width="2" name="op1" settings="2">
<c>0</c>
<c>0</c>
</box>
<box hibit="22" name="D" usename="1">
<c></c>
</box>
<box hibit="21" width="2" name="op2" settings="2">
<c>0</c>
<c>0</c>
</box>
<box hibit="19" width="4" name="Vn" usename="1">
<c colspan="4"></c>
</box>
<box hibit="15" width="4" name="Vd" usename="1">
<c colspan="4"></c>
</box>
<box hibit="11" settings="1">
<c>1</c>
</box>
<box hibit="10" name="op3" settings="1">
<c>1</c>
</box>
<box hibit="9" settings="1">
<c>0</c>
</box>
<box hibit="8" name="op4" settings="1">
<c>1</c>
</box>
<box hibit="7" name="N" usename="1">
<c></c>
</box>
<box hibit="6" name="Q" usename="1">
<c></c>
</box>
<box hibit="5" name="M" usename="1">
<c></c>
</box>
<box hibit="4" name="U" settings="1">
<c>0</c>
</box>
<box hibit="3" width="4" name="Vm" usename="1">
<c colspan="4"></c>
</box>
</regdiagram>
<encoding name="VDOT_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
<docvars>
<docvar key="armarmheading" value="A1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="A32" />
<docvar key="mnemonic" value="VDOT" />
<docvar key="simdvectorsize" value="double" />
</docvars>
<box hibit="6" width="1" name="Q">
<c>0</c>
</box>
<asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
</encoding>
<encoding name="VDOT_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
<docvars>
<docvar key="armarmheading" value="A1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="A32" />
<docvar key="mnemonic" value="VDOT" />
<docvar key="simdvectorsize" value="quad" />
</docvars>
<box hibit="6" width="1" name="Q">
<c>1</c>
</box>
<asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="aarch32/instrs/VDOT_bf16/A1_A.txt" mylink="aarch32.instrs.VDOT_bf16.A1_A.txt" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;
if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
integer regs = if Q == '1' then 2 else 1;</pstext>
</ps>
</ps_section>
</iclass>
<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
<docvars>
<docvar key="armarmheading" value="T1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="T32" />
<docvar key="mnemonic" value="VDOT" />
</docvars>
<iclassintro count="2"></iclassintro>
<arch_variants>
<arch_variant name="ARMv8.6" feature="FEAT_AA32BF16" />
</arch_variants>
<regdiagram form="16x2" psname="aarch32/instrs/VDOT_bf16/T1_A.txt">
<box hibit="31" width="7" settings="7">
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>1</c>
<c>0</c>
</box>
<box hibit="24" width="2" name="op1" settings="2">
<c>0</c>
<c>0</c>
</box>
<box hibit="22" name="D" usename="1">
<c></c>
</box>
<box hibit="21" width="2" name="op2" settings="2">
<c>0</c>
<c>0</c>
</box>
<box hibit="19" width="4" name="Vn" usename="1">
<c colspan="4"></c>
</box>
<box hibit="15" width="4" name="Vd" usename="1">
<c colspan="4"></c>
</box>
<box hibit="11" settings="1">
<c>1</c>
</box>
<box hibit="10" name="op3" settings="1">
<c>1</c>
</box>
<box hibit="9" settings="1">
<c>0</c>
</box>
<box hibit="8" name="op4" settings="1">
<c>1</c>
</box>
<box hibit="7" name="N" usename="1">
<c></c>
</box>
<box hibit="6" name="Q" usename="1">
<c></c>
</box>
<box hibit="5" name="M" usename="1">
<c></c>
</box>
<box hibit="4" name="U" settings="1">
<c>0</c>
</box>
<box hibit="3" width="4" name="Vm" usename="1">
<c colspan="4"></c>
</box>
</regdiagram>
<encoding name="VDOT_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="Q == 0">
<docvars>
<docvar key="armarmheading" value="T1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="T32" />
<docvar key="mnemonic" value="VDOT" />
<docvar key="simdvectorsize" value="double" />
</docvars>
<box hibit="6" width="1" name="Q">
<c>0</c>
</box>
<asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_dd" hover="64-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Dd&gt;</a><text>, </text><a link="sa_dn" hover="First 64-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Dn&gt;</a><text>, </text><a link="sa_dm" hover="Second 64-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Dm&gt;</a></asmtemplate>
</encoding>
<encoding name="VDOT_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="Q == 1">
<docvars>
<docvar key="armarmheading" value="T1" />
<docvar key="instr-class" value="fpsimd" />
<docvar key="isa" value="T32" />
<docvar key="mnemonic" value="VDOT" />
<docvar key="simdvectorsize" value="quad" />
</docvars>
<box hibit="6" width="1" name="Q">
<c>1</c>
</box>
<asmtemplate><text>VDOT</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}">&lt;q&gt;</a><text>}</text><text>.BF16 </text><a link="sa_qd" hover="128-bit SIMD&amp;FP destination register (field &quot;D:Vd&quot;)">&lt;Qd&gt;</a><text>, </text><a link="sa_qn" hover="First 128-bit SIMD&amp;FP source register (field &quot;N:Vn&quot;)">&lt;Qn&gt;</a><text>, </text><a link="sa_qm" hover="Second 128-bit SIMD&amp;FP source register (field &quot;M:Vm&quot;)">&lt;Qm&gt;</a></asmtemplate>
</encoding>
<ps_section howmany="1">
<ps name="aarch32/instrs/VDOT_bf16/T1_A.txt" mylink="aarch32.instrs.VDOT_bf16.T1_A.txt" enclabels="" sections="1" secttype="noheading">
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() then UNPREDICTABLE;
if !<a link="impl-shared.HaveAArch32BF16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveAArch32BF16Ext()">HaveAArch32BF16Ext</a>() then UNDEFINED;
if Q == '1' &amp;&amp; (Vd&lt;0&gt; == '1' || Vn&lt;0&gt; == '1' || Vm&lt;0&gt; == '1') then UNDEFINED;
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(N:Vn);
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm);
integer regs = if Q == '1' then 2 else 1;</pstext>
</ps>
</ps_section>
</iclass>
</classes>
<explanations scope="all">
<explanation enclist="VDOT_A1_D, VDOT_T1_D" symboldefcount="1">
<symbol link="sa_q">&lt;q&gt;</symbol>
<account encodedin="">
<intro>
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
</intro>
</account>
</explanation>
<explanation enclist="VDOT_A1_Q, VDOT_T1_Q" symboldefcount="1">
<symbol link="sa_qd">&lt;Qd&gt;</symbol>
<account encodedin="D:Vd">
<intro>
<para>Is the 128-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field as &lt;Qd&gt;*2.</para>
</intro>
</account>
</explanation>
<explanation enclist="VDOT_A1_Q, VDOT_T1_Q" symboldefcount="1">
<symbol link="sa_qn">&lt;Qn&gt;</symbol>
<account encodedin="N:Vn">
<intro>
<para>Is the 128-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field as &lt;Qn&gt;*2.</para>
</intro>
</account>
</explanation>
<explanation enclist="VDOT_A1_Q, VDOT_T1_Q" symboldefcount="1">
<symbol link="sa_qm">&lt;Qm&gt;</symbol>
<account encodedin="M:Vm">
<intro>
<para>Is the 128-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field as &lt;Qm&gt;*2.</para>
</intro>
</account>
</explanation>
<explanation enclist="VDOT_A1_D, VDOT_T1_D" symboldefcount="1">
<symbol link="sa_dd">&lt;Dd&gt;</symbol>
<account encodedin="D:Vd">
<intro>
<para>Is the 64-bit name of the SIMD&amp;FP destination register, encoded in the "D:Vd" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="VDOT_A1_D, VDOT_T1_D" symboldefcount="1">
<symbol link="sa_dn">&lt;Dn&gt;</symbol>
<account encodedin="N:Vn">
<intro>
<para>Is the 64-bit name of the first SIMD&amp;FP source register, encoded in the "N:Vn" field.</para>
</intro>
</account>
</explanation>
<explanation enclist="VDOT_A1_D, VDOT_T1_D" symboldefcount="1">
<symbol link="sa_dm">&lt;Dm&gt;</symbol>
<account encodedin="M:Vm">
<intro>
<para>Is the 64-bit name of the second SIMD&amp;FP source register, encoded in the "M:Vm" field.</para>
</intro>
</account>
</explanation>
</explanations>
<ps_section howmany="1">
<ps name="aarch32/instrs/VDOT_bf16/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) operand1;
bits(64) operand2;
bits(64) result;
<a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
for r = 0 to regs-1
operand1 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[n+r];
operand2 = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[m+r];
result = <a link="impl-aarch32.Din.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) Din[integer n]">Din</a>[d+r];
for e = 0 to 1
bits(16) elt1_a = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 0, 16];
bits(16) elt1_b = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 1, 16];
bits(16) elt2_a = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + 0, 16];
bits(16) elt2_b = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + 1, 16];
bits(32) sum = <a link="impl-shared.FPAdd_BF16.2" file="shared_pseudocode.xml" hover="function: bits(32) FPAdd_BF16(bits(32) op1, bits(32) op2)">FPAdd_BF16</a>(<a link="impl-shared.BFMulH.2" file="shared_pseudocode.xml" hover="function: bits(32) BFMulH(bits(16) op1, bits(16) op2)">BFMulH</a>(elt1_a, elt2_a), <a link="impl-shared.BFMulH.2" file="shared_pseudocode.xml" hover="function: bits(32) BFMulH(bits(16) op1, bits(16) op2)">BFMulH</a>(elt1_b, elt2_b));
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = <a link="impl-shared.FPAdd_BF16.2" file="shared_pseudocode.xml" hover="function: bits(32) FPAdd_BF16(bits(32) op1, bits(32) op2)">FPAdd_BF16</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, e, 32], sum);
<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = result;</pstext>
</ps>
</ps_section>
</instructionsection>
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