475 lines
25 KiB
XML
475 lines
25 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VCVT_xs" title="VCVT (between floating-point and fixed-point, Advanced SIMD) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VCVT" />
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</docvars>
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<heading>VCVT (between floating-point and fixed-point, Advanced SIMD)</heading>
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<desc>
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<brief>
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<para>Vector Convert between floating-point and fixed-point</para>
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</brief>
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<authored>
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<para>Vector Convert between floating-point and fixed-point converts each element in a vector from floating-point to fixed-point, or from fixed-point to floating-point, and places the results in a second vector.</para>
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<para>The vector elements are the same type, and are floating-point numbers or integers. Signed and unsigned integers are distinct.</para>
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<para>The floating-point to fixed-point operation uses the Round towards Zero rounding mode. The fixed-point to floating-point operation uses the Round to Nearest rounding mode.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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<encodingnotes>
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<para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
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</encodingnotes>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VCVT" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VCVT_xs/A1_A.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="23" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="6" name="imm6" usename="1">
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<c colspan="6"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="2" name="op" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="7" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VCVT_xs_A1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="imm6 != 000xxx && Q == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VCVT" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="21" width="6" name="imm6">
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c></c>
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<c></c>
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<c></c>
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</box>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VCVT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field "op:U")"><dt1></a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field "op:U")"><dt2></a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dm" hover="64-bit SIMD&FP source register (field "M:Vm")"><Dm></a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed point number [1-32 for 32-bit elements]"><fbits></a></asmtemplate>
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</encoding>
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<encoding name="VCVT_xs_A1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="imm6 != 000xxx && Q == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VCVT" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="21" width="6" name="imm6">
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c></c>
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<c></c>
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<c></c>
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</box>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VCVT</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field "op:U")"><dt1></a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field "op:U")"><dt2></a><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qm" hover="128-bit SIMD&FP source register (field "M:Vm")"><Qm></a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed point number [1-32 for 32-bit elements]"><fbits></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VCVT_xs/A1_A.txt" mylink="aarch32.instrs.VCVT_xs.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if imm6 IN {'000xxx'} then SEE "Related encodings";
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if op<1> == '0' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
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if op<1> == '0' && imm6 IN {'10xxxx'} then UNDEFINED;
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if imm6 IN {'0xxxxx'} then UNDEFINED;
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if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
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to_fixed = (op<0> == '1'); frac_bits = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
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unsigned = (U == '1');
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integer esize;
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integer elements;
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case op<1> of
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when '0' esize = 16; elements = 4;
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when '1' esize = 32; elements = 2;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VCVT" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VCVT_xs/T1_A.txt">
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<box hibit="31" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="28" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="6" name="imm6" usename="1">
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<c colspan="6"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="9" width="2" name="op" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="7" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VCVT_xs_T1_D" oneofinclass="2" oneof="4" label="64-bit SIMD vector" bitdiffs="imm6 != 000xxx && Q == 0">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VCVT" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="21" width="6" name="imm6">
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c></c>
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<c></c>
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<c></c>
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</box>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field "op:U")"><dt1></a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field "op:U")"><dt2></a><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_dm" hover="64-bit SIMD&FP source register (field "M:Vm")"><Dm></a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed point number [1-32 for 32-bit elements]"><fbits></a></asmtemplate>
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</encoding>
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<encoding name="VCVT_xs_T1_Q" oneofinclass="2" oneof="4" label="128-bit SIMD vector" bitdiffs="imm6 != 000xxx && Q == 1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VCVT" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="21" width="6" name="imm6">
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c></c>
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<c></c>
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<c></c>
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</box>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.</text><a link="sa_dt1" hover="Data type for elements of destination vector (field "op:U")"><dt1></a><text>.</text><a link="sa_dt2" hover="Data type for elements of source vector (field "op:U")"><dt2></a><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, </text><a link="sa_qm" hover="128-bit SIMD&FP source register (field "M:Vm")"><Qm></a><text>, #</text><a link="sa_fbits" hover="The number of fraction bits in the fixed point number [1-32 for 32-bit elements]"><fbits></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VCVT_xs/T1_A.txt" mylink="aarch32.instrs.VCVT_xs.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if imm6 IN {'000xxx'} then SEE "Related encodings";
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if op<1> == '0' && !<a link="impl-shared.HaveFP16Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveFP16Ext()">HaveFP16Ext</a>() then UNDEFINED;
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if op<1> == '0' && imm6 IN {'10xxxx'} then UNDEFINED;
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if imm6 IN {'0xxxxx'} then UNDEFINED;
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if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
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to_fixed = (op<0> == '1'); frac_bits = 64 - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
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unsigned = (U == '1');
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integer esize;
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integer elements;
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case op<1> of
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when '0' esize = 16; elements = 4;
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when '1' esize = 32; elements = 2;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm); regs = if Q == '0' then 1 else 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VCVT_xs_A1_Q" symboldefcount="1">
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<symbol link="sa_c_1"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VCVT_xs_T1_Q" symboldefcount="2">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
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<symbol link="sa_dt1"><dt1></symbol>
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<definition encodedin="op:U">
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<intro>Is the data type for the elements of the destination vector, </intro>
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<table class="valuetable">
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<tgroup cols="3">
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<thead>
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<row>
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<entry class="bitfield">op</entry>
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<entry class="bitfield">U</entry>
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<entry class="symbol"><dt1></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="bitfield">x</entry>
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<entry class="symbol">F16</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="bitfield">0</entry>
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<entry class="symbol">S16</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="bitfield">1</entry>
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<entry class="symbol">U16</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="bitfield">x</entry>
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|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</explanation>
|
|
<explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_dt2"><dt2></symbol>
|
|
<definition encodedin="op:U">
|
|
<intro>Is the data type for the elements of the source vector, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="3">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">op</entry>
|
|
<entry class="bitfield">U</entry>
|
|
<entry class="symbol"><dt2></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">00</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">01</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">F16</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">S32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">10</entry>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">U32</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">11</entry>
|
|
<entry class="bitfield">x</entry>
|
|
<entry class="symbol">F32</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</explanation>
|
|
<explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_qd"><Qd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_qm"><Qm></symbol>
|
|
<account encodedin="M:Vm">
|
|
<intro>
|
|
<para>Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VCVT_xs_A1_D, VCVT_xs_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dd"><Dd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VCVT_xs_A1_D, VCVT_xs_T1_D" symboldefcount="1">
|
|
<symbol link="sa_dm"><Dm></symbol>
|
|
<account encodedin="M:Vm">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VCVT_xs_A1_Q, VCVT_xs_T1_Q" symboldefcount="1">
|
|
<symbol link="sa_fbits"><fbits></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>The number of fraction bits in the fixed point number, in the range 1 to 32 for 32-bit elements, or in the range 1 to 16 for 16-bit elements:</para>
|
|
<list type="unordered">
|
|
<listitem><content>(64 - <syntax><fbits></syntax>) is encoded in imm6.</content></listitem>
|
|
</list>
|
|
<para>An assembler can permit an <syntax><fbits></syntax> value of 0. This is encoded as floating-point to integer or integer to floating-point instruction, see <xref linkend="A32T32-fpsimd.instructions.VCVT_is">VCVT (between floating-point and integer, Advanced SIMD)</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
<arch_variants>
|
|
<arch_variant name="ARMv8.2-A" />
|
|
</arch_variants>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VCVT_xs/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
|
|
bits(esize) result;
|
|
for r = 0 to regs-1
|
|
for e = 0 to elements-1
|
|
op1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m+r],e,esize];
|
|
if to_fixed then
|
|
result = <a link="impl-shared.FPToFixed.6" file="shared_pseudocode.xml" hover="function: bits(M) FPToFixed(bits(N) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer M)">FPToFixed</a>(op1, frac_bits, unsigned, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(),
|
|
<a link="FPRounding_ZERO" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_ZERO</a>, esize);
|
|
else
|
|
result = <a link="impl-shared.FixedToFP.6" file="shared_pseudocode.xml" hover="function: bits(N) FixedToFP(bits(M) op, integer fbits, boolean unsigned, FPCRType fpcr, FPRounding rounding, integer N)">FixedToFP</a>(op1, frac_bits, unsigned, <a link="impl-aarch32.StandardFPSCRValue.0" file="shared_pseudocode.xml" hover="function: FPCRType StandardFPSCRValue()">StandardFPSCRValue</a>(),
|
|
<a link="FPRounding_TIEEVEN" file="shared_pseudocode.xml" hover="enumeration FPRounding {FPRounding_TIEEVEN, FPRounding_POSINF, FPRounding_NEGINF, FPRounding_ZERO, FPRounding_TIEAWAY, FPRounding_ODD}">FPRounding_TIEEVEN</a>, esize);
|
|
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r],e,esize] = result;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|