295 lines
15 KiB
XML
295 lines
15 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VCVT_ds" title="VCVT (between double-precision and single-precision) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VCVT" />
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</docvars>
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<heading>VCVT (between double-precision and single-precision)</heading>
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<desc>
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<brief>
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<para>Convert between double-precision and single-precision</para>
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</brief>
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<authored>
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<para>Convert between double-precision and single-precision does one of the following:</para>
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<list type="unordered">
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<listitem><content>Converts the value in a double-precision register to single-precision and writes the result to a single-precision register.</content></listitem>
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<listitem><content>Converts the value in a single-precision register to double-precision and writes the result to a double-precision register.</content></listitem>
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</list>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, <xref linkend="AArch32.hcptr">HCPTR</xref>, and <xref linkend="AArch32.fpexc">FPEXC</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VCVT" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VCVT_ds/T1A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="19" name="o1" settings="1">
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<c>0</c>
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</box>
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<box hibit="18" width="3" name="opc2" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" usename="1" settings="1">
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<c>1</c>
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<c>x</c>
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</box>
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<box hibit="7" name="o3" settings="1">
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<c>1</c>
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</box>
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<box hibit="6" settings="1">
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<c>1</c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VCVT_ds_A1" oneofinclass="2" oneof="4" label="Single-precision to double-precision" bitdiffs="size == 10">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="convert-type" value="single-to-double" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VCVT" />
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</docvars>
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<box hibit="9" width="" name="size">
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<c></c>
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<c>0</c>
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</box>
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<asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F64.F32 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_sm" hover="32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VCVT_sd_A1" oneofinclass="2" oneof="4" label="Double-precision to single-precision" bitdiffs="size == 11">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="convert-type" value="double-to-single" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VCVT" />
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</docvars>
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<box hibit="9" width="" name="size">
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<c></c>
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<c>1</c>
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</box>
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<asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F32.F64 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_dm" hover="64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VCVT_ds/T1A1_A.txt" mylink="aarch32.instrs.VCVT_ds.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">double_to_single = (size == '11');
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d = if double_to_single then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
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m = if double_to_single then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VCVT" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VCVT_ds/T1A1_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="19" name="o1" settings="1">
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<c>0</c>
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</box>
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<box hibit="18" width="3" name="opc2" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="9" width="2" name="size" usename="1" settings="1">
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<c>1</c>
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<c>x</c>
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</box>
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<box hibit="7" name="o3" settings="1">
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<c>1</c>
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</box>
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<box hibit="6" settings="1">
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<c>1</c>
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</box>
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<box hibit="5" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Vm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VCVT_ds_T1" oneofinclass="2" oneof="4" label="Single-precision to double-precision" bitdiffs="size == 10">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="convert-type" value="single-to-double" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VCVT" />
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</docvars>
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<box hibit="9" width="" name="size">
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<c></c>
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<c>0</c>
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</box>
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<asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F64.F32 </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, </text><a link="sa_sm" hover="32-bit SIMD&FP source register (field "Vm:M")"><Sm></a></asmtemplate>
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</encoding>
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<encoding name="VCVT_sd_T1" oneofinclass="2" oneof="4" label="Double-precision to single-precision" bitdiffs="size == 11">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="convert-type" value="double-to-single" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VCVT" />
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</docvars>
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<box hibit="9" width="" name="size">
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<c></c>
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<c>1</c>
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</box>
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<asmtemplate><text>VCVT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.F32.F64 </text><a link="sa_sd" hover="32-bit SIMD&FP destination register (field "Vd:D")"><Sd></a><text>, </text><a link="sa_dm" hover="64-bit SIMD&FP source register (field "M:Vm")"><Dm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VCVT_ds/T1A1_A.txt" mylink="aarch32.instrs.VCVT_ds.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">double_to_single = (size == '11');
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d = if double_to_single then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd:D) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd);
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m = if double_to_single then <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(M:Vm) else <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vm:M);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="VCVT_ds_A1, VCVT_ds_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VCVT_ds_A1, VCVT_ds_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VCVT_sd_A1, VCVT_sd_T1" symboldefcount="1">
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<symbol link="sa_sd"><Sd></symbol>
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<account encodedin="Vd:D">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VCVT_sd_A1, VCVT_sd_T1" symboldefcount="1">
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<symbol link="sa_dm"><Dm></symbol>
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<account encodedin="M:Vm">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VCVT_ds_A1, VCVT_ds_T1" symboldefcount="1">
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<symbol link="sa_dd"><Dd></symbol>
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<account encodedin="D:Vd">
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<intro>
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<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="VCVT_ds_A1, VCVT_ds_T1" symboldefcount="1">
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<symbol link="sa_sm"><Sm></symbol>
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<account encodedin="Vm:M">
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<intro>
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<para>Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VCVT_ds/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations(); <a link="impl-aarch32.CheckVFPEnabled.1" file="shared_pseudocode.xml" hover="function: CheckVFPEnabled(boolean include_fpexc_check)">CheckVFPEnabled</a>(TRUE);
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if double_to_single then
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<a link="impl-aarch32.S.write.1" file="shared_pseudocode.xml" hover="accessor: S[integer n] = bits(32) value">S</a>[d] = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(<a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[m], FPSCR[], 32);
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else
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<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d] = <a link="impl-shared.FPConvert.3" file="shared_pseudocode.xml" hover="function: bits(M) FPConvert(bits(N) op, FPCRType fpcr, integer M)">FPConvert</a>(<a link="impl-aarch32.S.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) S[integer n]">S</a>[m], FPSCR[], 64);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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