509 lines
27 KiB
XML
509 lines
27 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="VBIC_i" title="VBIC (immediate) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="mnemonic" value="VBIC" />
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</docvars>
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<heading>VBIC (immediate)</heading>
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<desc>
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<brief>
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<para>Vector Bitwise Bit Clear (immediate)</para>
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</brief>
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<authored>
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<para>Vector Bitwise Bit Clear (immediate) performs a bitwise AND between a register value and the complement of an immediate value, and returns the result into the destination vector.</para>
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<para>Depending on settings in the <xref linkend="AArch32.cpacr">CPACR</xref>, <xref linkend="AArch32.nsacr">NSACR</xref>, and <xref linkend="AArch32.hcptr">HCPTR</xref> registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be <arm-defined-word>undefined</arm-defined-word>, or trapped to Hyp mode. For more information see <xref linkend="CIHIDDFF">Enabling Advanced SIMD and floating-point support</xref>.</para>
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</authored>
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<encodingnotes>
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<para>Related encodings: See <xref linkend="T32.encoding_index.simd_1r_imm">Advanced SIMD one register and modified immediate</xref> for the T32 instruction set, or <xref linkend="A32.encoding_index.simd1reg_imm">Advanced SIMD one register and modified immediate</xref> for the A32 instruction set.</para>
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</encodingnotes>
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<syntaxnotes>
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<para>The I8, I64, and F32 data types are permitted as pseudo-instructions, if the immediate can be represented by this instruction, and are encoded using a permitted encoding of the I16 or I32 data type.</para>
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</syntaxnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1 and this instruction passes its condition execution check:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="1">
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<alias_list_intro>This instruction is used by the alias </alias_list_intro>
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<aliasref aliaspageid="VAND_VBIC_i" aliasfile="vand_vbic_i.xml" hover="Vector Bitwise AND (immediate)" punct=".">
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<text>VAND (immediate)</text>
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<aliaspref>Never</aliaspref>
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</aliasref>
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<alias_list_outro>
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<text> See </text>
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<aliastablelink />
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<text> below for details of when the alias is preferred.</text>
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</alias_list_outro>
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</alias_list>
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<classes>
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<classesintro count="4">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt> and </txt>
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<a href="#iclass_a2">A2</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t2">T2</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VBIC" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VBIC_i/T1A1_A.txt" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" name="i" usename="1">
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<c></c>
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</box>
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<box hibit="23" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="18" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="cmode" usename="1" settings="2">
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<c>0</c>
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<c>x</c>
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<c>x</c>
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<c>1</c>
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</box>
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<box hibit="7" settings="1">
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<c>0</c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="op" settings="1">
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<c>1</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="imm4" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VBIC_i_A1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VBIC" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VBIC</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I32 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
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</encoding>
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<encoding name="VBIC_i_A1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VBIC" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VBIC</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I32 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VBIC_i/T1A1_A.txt" mylink="aarch32.instrs.VBIC_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if cmode<0> == '0' || cmode<3:2> == '11' then SEE "Related encodings";
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if Q == '1' && Vd<0> == '1' then UNDEFINED;
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imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="A2" oneof="4" id="iclass_a2" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VBIC" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/VBIC_i/T2A2_A.txt" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" name="i" usename="1">
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<c></c>
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</box>
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<box hibit="23" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="18" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="cmode" usename="1" settings="3">
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<c>1</c>
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<c>0</c>
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<c>x</c>
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<c>1</c>
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</box>
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<box hibit="7" settings="1">
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<c>0</c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="op" settings="1">
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<c>1</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="imm4" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VBIC_i_A2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VBIC" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VBIC</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I16 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
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</encoding>
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<encoding name="VBIC_i_A2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="armarmheading" value="A2" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="VBIC" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>1</c>
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</box>
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<asmtemplate><text>VBIC</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I16 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/VBIC_i/T2A2_A.txt" mylink="aarch32.instrs.VBIC_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if cmode<0> == '0' || cmode<3:2> == '11' then SEE "Related encodings";
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if Q == '1' && Vd<0> == '1' then UNDEFINED;
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imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="4" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VBIC" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/VBIC_i/T1A1_A.txt" tworows="1">
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<box hibit="31" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="28" name="i" usename="1">
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<c></c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" name="D" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="18" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="15" width="4" name="Vd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="cmode" usename="1" settings="2">
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<c>0</c>
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<c>x</c>
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<c>x</c>
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<c>1</c>
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</box>
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<box hibit="7" settings="1">
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<c>0</c>
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</box>
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<box hibit="6" name="Q" usename="1">
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<c></c>
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</box>
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<box hibit="5" name="op" settings="1">
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<c>1</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="imm4" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="VBIC_i_T1_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VBIC" />
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<docvar key="simdvectorsize" value="double" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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<c>0</c>
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</box>
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<asmtemplate><text>VBIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I32 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
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</encoding>
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<encoding name="VBIC_i_T1_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="fpsimd" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="VBIC" />
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<docvar key="simdvectorsize" value="quad" />
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</docvars>
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<box hibit="6" width="1" name="Q">
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|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VBIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I32 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VBIC_i/T1A1_A.txt" mylink="aarch32.instrs.VBIC_i.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if cmode<0> == '0' || cmode<3:2> == '11' then SEE "Related encodings";
|
|
if Q == '1' && Vd<0> == '1' then UNDEFINED;
|
|
imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VBIC" />
|
|
</docvars>
|
|
<iclassintro count="2"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/VBIC_i/T2A2_A.txt" tworows="1">
|
|
<box hibit="31" width="3" settings="3">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="28" name="i" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="27" width="5" settings="5">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="22" name="D" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" width="3" settings="3">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="18" width="3" name="imm3" usename="1">
|
|
<c colspan="3"></c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Vd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" width="4" name="cmode" usename="1" settings="3">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>x</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="7" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="6" name="Q" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="5" name="op" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="imm4" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="VBIC_i_T2_D" oneofinclass="2" oneof="8" label="64-bit SIMD vector" bitdiffs="Q == 0">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VBIC" />
|
|
<docvar key="simdvectorsize" value="double" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>VBIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I16 </text><text>{</text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>,</text><text>}</text><text> </text><a link="sa_dd" hover="64-bit SIMD&FP destination register (field "D:Vd")"><Dd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="VBIC_i_T2_Q" oneofinclass="2" oneof="8" label="128-bit SIMD vector" bitdiffs="Q == 1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="fpsimd" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="VBIC" />
|
|
<docvar key="simdvectorsize" value="quad" />
|
|
</docvars>
|
|
<box hibit="6" width="1" name="Q">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>VBIC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text>.I16 </text><text>{</text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>,</text><text>}</text><text> </text><a link="sa_qd" hover="128-bit SIMD&FP destination register (field "D:Vd")"><Qd></a><text>, #</text><a link="sa_imm" hover="Constant of specified type that is replicated to fill the destination register"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VBIC_i/T2A2_A.txt" mylink="aarch32.instrs.VBIC_i.T2A2_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if cmode<0> == '0' || cmode<3:2> == '11' then SEE "Related encodings";
|
|
if Q == '1' && Vd<0> == '1' then UNDEFINED;
|
|
imm64 = <a link="impl-shared.AdvSIMDExpandImm.3" file="shared_pseudocode.xml" hover="function: bits(64) AdvSIMDExpandImm(bit op, bits(4) cmode, bits(8) imm8)">AdvSIMDExpandImm</a>('1', cmode, i:imm3:imm4);
|
|
d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(D:Vd); regs = if Q == '0' then 1 else 2;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="VBIC_i_A1_Q, VBIC_i_A2_Q" symboldefcount="1">
|
|
<symbol link="sa_c_1"><c></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1 and A2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. This encoding must be unconditional.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VBIC_i_T1_Q, VBIC_i_T2_Q" symboldefcount="2">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VBIC_i_A1_Q, VBIC_i_A2_Q, VBIC_i_T1_Q, VBIC_i_T2_Q" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VBIC_i_A1_Q, VBIC_i_A2_Q, VBIC_i_T1_Q, VBIC_i_T2_Q" symboldefcount="1">
|
|
<symbol link="sa_qd"><Qd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VBIC_i_A1_D, VBIC_i_A2_D, VBIC_i_T1_D, VBIC_i_T2_D" symboldefcount="1">
|
|
<symbol link="sa_dd"><Dd></symbol>
|
|
<account encodedin="D:Vd">
|
|
<intro>
|
|
<para>Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="VBIC_i_A1_Q, VBIC_i_A2_Q, VBIC_i_T1_Q, VBIC_i_T2_Q" symboldefcount="1">
|
|
<symbol link="sa_imm"><imm></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Is a constant of the specified type that is replicated to fill the destination register. For details of the range of constants available and the encoding of <syntax><imm></syntax>, see <xref linkend="CJAIDJDJ">Modified immediate constants in T32 and A32 Advanced SIMD instructions</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/VBIC_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations(); <a link="impl-aarch32.CheckAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: CheckAdvSIMDEnabled()">CheckAdvSIMDEnabled</a>();
|
|
for r = 0 to regs-1
|
|
<a link="impl-aarch32.D.write.1" file="shared_pseudocode.xml" hover="accessor: D[integer n] = bits(64) value">D</a>[d+r] = <a link="impl-aarch32.D.read.1" file="shared_pseudocode.xml" hover="accessor: bits(64) D[integer n]">D</a>[d+r] AND NOT(imm64);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|