185 lines
10 KiB
XML
185 lines
10 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="TBB" title="TBB, TBH -- AArch32" type="instruction">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<heading>TBB, TBH</heading>
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<desc>
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<brief>
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<para>Table Branch Byte or Halfword</para>
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</brief>
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<authored>
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<para>Table Branch Byte or Halfword causes a PC-relative forward branch using a table of single byte or halfword offsets. A base register provides a pointer to the table, and a second register supplies an index into the table. The branch length is twice the value returned from the table.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="T1" oneof="1" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/TBB/T1_A.txt">
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<box hibit="31" width="12" settings="12">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="14" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="13" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="12" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="11" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="10" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="9" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="8" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="7" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="4" name="H" usename="1">
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<c></c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="TBB_T1" oneofinclass="2" oneof="2" label="Byte" bitdiffs="H == 0">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="loadstore-size" value="ls-byte" />
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<docvar key="mnemonic" value="TBB" />
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</docvars>
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<box hibit="4" width="1" name="H">
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<c>0</c>
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</box>
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<asmtemplate comment="Outside or last in IT block"><text>TBB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register holding address of table of branch lengths (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="General-purpose index register (field "Rm")"><Rm></a><text>]</text></asmtemplate>
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</encoding>
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<encoding name="TBH_T1" oneofinclass="2" oneof="2" label="Halfword" bitdiffs="H == 1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="loadstore-size" value="ls-halfword" />
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<docvar key="mnemonic" value="TBH" />
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</docvars>
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<box hibit="4" width="1" name="H">
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<c>1</c>
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</box>
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<asmtemplate comment="Outside or last in IT block"><text>TBH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register holding address of table of branch lengths (field "Rn")"><Rn></a><text>, </text><a link="sa_rm_1" hover="General-purpose index register (field "Rm")"><Rm></a><text>, LSL #1]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/TBB/T1_A.txt" mylink="aarch32.instrs.TBB.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm); is_tbh = (H == '1');
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if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
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if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() && !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="TBB_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TBB_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TBB_T1" symboldefcount="1">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the general-purpose base register holding the address of the table of branch lengths, encoded in the "Rn" field. The PC can be used. If it is, the table immediately follows this instruction.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TBB_T1" symboldefcount="1">
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<symbol link="sa_rm"><Rm></symbol>
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<account encodedin="Rm">
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<docvars>
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<docvar key="loadstore-size" value="ls-byte" />
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<docvar key="mnemonic" value="TBB" />
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</docvars>
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<intro>
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<para>For the byte variant: is the general-purpose index register, encoded in the "Rm" field. This register contains an integer pointing to a single byte in the table. The offset in the table is the value of the index.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="TBH_T1" symboldefcount="2">
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<symbol link="sa_rm_1"><Rm></symbol>
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<account encodedin="Rm">
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<docvars>
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<docvar key="loadstore-size" value="ls-halfword" />
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<docvar key="mnemonic" value="TBH" />
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</docvars>
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<intro>
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<para>For the halfword variant: is the general-purpose index register, encoded in the "Rm" field. This register contains an integer pointing to a halfword in the table. The offset in the table is twice the value of the index.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/TBB/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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integer halfwords;
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if is_tbh then
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halfwords = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+<a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m],1), 2]);
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else
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halfwords = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], 1]);
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<a link="impl-aarch32.BranchWritePC.2" file="shared_pseudocode.xml" hover="function: BranchWritePC(bits(32) address_in, BranchType branch_type)">BranchWritePC</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a> + 2*halfwords, <a link="BranchType_INDIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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