425 lines
23 KiB
XML
425 lines
23 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="SUB_SP_i" title="SUB, SUBS (SP minus immediate) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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</docvars>
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<heading>SUB, SUBS (SP minus immediate)</heading>
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<desc>
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<brief>
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<para>Subtract from SP (immediate)</para>
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</brief>
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<authored>
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<para>Subtract from SP (immediate) subtracts an immediate value from the SP value, and writes the result to the destination register.</para>
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<para>If the destination register is not the PC, the SUBS variant of the instruction updates the condition flags based on the result.</para>
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<para>The field descriptions for <syntax><Rd></syntax> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:</para>
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<list type="unordered">
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<listitem><content>The SUB variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
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<listitem><content>The SUBS variant of the instruction performs an exception return without the use of the stack. Arm deprecates use of this instruction. However, in this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_<current_mode>.</content></listitem><listitem><content>The PE checks SPSR_<current_mode> for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
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</list>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="4">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>, </txt>
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<a href="#iclass_t2">T2</a>
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<txt> and </txt>
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<a href="#iclass_t3">T3</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="4" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/SUB_SP_i/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="4" settings="4">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="3" name="opc" settings="3">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="20" name="S" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rn" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="SUB_SP_i_A1" oneofinclass="2" oneof="6" label="SUB" bitdiffs="S == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="SUB" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>0</c>
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</box>
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<asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const_1" hover="An immediate value"><const></a></asmtemplate>
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</encoding>
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<encoding name="SUBS_SP_i_A1" oneofinclass="2" oneof="6" label="SUBS" bitdiffs="S == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="SUBS" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>1</c>
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</box>
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<asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd_1" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const_1" hover="An immediate value"><const></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/SUB_SP_i/A1_A.txt" mylink="aarch32.instrs.SUB_SP_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); setflags = (S == '1'); imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="SUB" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16" psname="aarch32/instrs/SUB_SP_i/T1_A.txt">
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<box hibit="31" width="8" settings="8">
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="S" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" width="7" name="imm7" usename="1">
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<c colspan="7"></c>
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</box>
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</regdiagram>
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<encoding name="SUB_SP_i_T1" oneofinclass="1" oneof="6" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="SUB" />
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</docvars>
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<asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_sp" hover="Stack pointer">{SP,}</a><text> SP, #</text><a link="sa_imm7" hover="Unsigned immediate, multiple of 4 [0-508] (field "imm7")"><imm7></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/SUB_SP_i/T1_A.txt" mylink="aarch32.instrs.SUB_SP_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = 13; setflags = FALSE; imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm7:'00', 32);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T2" oneof="4" id="iclass_t2" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/SUB_SP_i/T2_A.txt">
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<box hibit="31" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="26" name="i" usename="1">
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<c></c>
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</box>
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<box hibit="25" settings="1">
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<c>0</c>
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</box>
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<box hibit="24" width="4" name="op1" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="20" name="S" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rn" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="11" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="SUB_SP_i_T2" oneofinclass="2" oneof="6" label="SUB" bitdiffs="S == 0">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="SUB" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>0</c>
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</box>
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<asmtemplate comment="<Rd>, <const> can be represented in T1"><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const" hover="An immediate value"><const></a></asmtemplate>
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<asmtemplate><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const" hover="An immediate value"><const></a></asmtemplate>
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</encoding>
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<encoding name="SUBS_SP_i_T2" oneofinclass="2" oneof="6" label="SUBS" bitdiffs="S == 1 && Rd != 1111">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="SUBS" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>1</c>
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</box>
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<box hibit="11" width="4" name="Rd">
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<c>N</c>
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<c>N</c>
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<c>N</c>
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<c>N</c>
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</box>
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<asmtemplate><text>SUBS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> SP, #</text><a link="sa_const" hover="An immediate value"><const></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/SUB_SP_i/T2_A.txt" mylink="aarch32.instrs.SUB_SP_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rd == '1111' && S == '1' then SEE "CMP (immediate)";
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); setflags = (S == '1'); imm32 = <a link="impl-aarch32.T32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) T32ExpandImm(bits(12) imm12)">T32ExpandImm</a>(i:imm3:imm8);
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if d == 15 && !setflags then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T3" oneof="4" id="iclass_t3" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T3" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="SUBW" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/SUB_SP_i/T3_A.txt">
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<box hibit="31" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="26" name="i" usename="1">
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<c></c>
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</box>
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<box hibit="25" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" name="o1" settings="1">
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<c>1</c>
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</box>
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<box hibit="22" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="o2" settings="1">
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<c>1</c>
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</box>
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<box hibit="20" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" settings="1">
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<c>0</c>
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</box>
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<box hibit="14" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="11" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="SUB_SP_i_T3" oneofinclass="1" oneof="6" label="T3">
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<docvars>
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<docvar key="armarmheading" value="T3" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="SUBW" />
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</docvars>
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<asmtemplate comment="<imm12> cannot be represented in T1, T2, or T3"><text>SUB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> SP, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field "i:imm3:imm8")"><imm12></a></asmtemplate>
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<asmtemplate comment="<imm12> can be represented in T1, T2, or T3"><text>SUBW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> SP, #</text><a link="sa_imm12" hover="12-bit unsigned immediate [0-4095] (field "i:imm3:imm8")"><imm12></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/SUB_SP_i/T3_A.txt" mylink="aarch32.instrs.SUB_SP_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); setflags = FALSE; imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(i:imm3:imm8, 32);
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if d == 15 then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="SUB_SP_i_A1, SUB_SP_i_T1, SUB_SP_i_T2, SUB_SP_i_T3" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="SUB_SP_i_A1, SUB_SP_i_T1, SUB_SP_i_T2, SUB_SP_i_T3" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
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|
</explanation>
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|
<explanation enclist="SUB_SP_i_T1" symboldefcount="1">
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|
<symbol link="sa_sp">SP,</symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Is the stack pointer.</para>
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|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SUB_SP_i_T1" symboldefcount="1">
|
|
<symbol link="sa_imm7"><imm7></symbol>
|
|
<account encodedin="imm7">
|
|
<intro>
|
|
<para>Is the unsigned immediate, a multiple of 4, in the range 0 to 508, encoded in the "imm7" field as <imm7>/4.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SUB_SP_i_A1" symboldefcount="1">
|
|
<symbol link="sa_rd_1"><Rd></symbol>
|
|
<account encodedin="Rd">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="SUB" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP. If the PC is used:</para>
|
|
<list type="unordered">
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|
<listitem><content>For the SUB variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
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|
<listitem><content>For the SUBS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_<current_mode>. Arm deprecates use of this instruction unless <syntax><Rn></syntax> is the LR.</content></listitem>
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|
</list>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SUB_SP_i_T2, SUB_SP_i_T3" symboldefcount="2">
|
|
<symbol link="sa_rd"><Rd></symbol>
|
|
<account encodedin="Rd">
|
|
<docvars>
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the SP.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SUB_SP_i_T3" symboldefcount="1">
|
|
<symbol link="sa_imm12"><imm12></symbol>
|
|
<account encodedin="i:imm3:imm8">
|
|
<intro>
|
|
<para>Is a 12-bit unsigned immediate, in the range 0 to 4095, encoded in the "i:imm3:imm8" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SUB_SP_i_A1" symboldefcount="1">
|
|
<symbol link="sa_const_1"><const></symbol>
|
|
<account encodedin="imm12">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="SUB_SP_i_T2" symboldefcount="2">
|
|
<symbol link="sa_const"><const></symbol>
|
|
<account encodedin="i:imm3:imm8">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T2: an immediate value. See <xref linkend="BABGHAGA">Modified immediate constants in T32 instructions</xref> for the range of values.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/SUB_SP_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[13], NOT(imm32), '1');
|
|
if d == 15 then // Can only occur for A32 encoding
|
|
if setflags then
|
|
<a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);
|
|
else
|
|
<a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);
|
|
else
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;
|
|
if setflags then
|
|
PSTATE.<N,Z,C,V> = nzcv;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|