316 lines
18 KiB
XML
316 lines
18 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="STRD_r" title="STRD (register) -- AArch32" type="instruction">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STRD" />
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</docvars>
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<heading>STRD (register)</heading>
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<desc>
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<brief>
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<para>Store Register Dual (register)</para>
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</brief>
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<authored>
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<para>Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="A1" oneof="1" id="iclass_a1" no_encodings="3" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STRD" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/STRD_r/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1">
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<c></c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="o1" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="10" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="9" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="8" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="7" settings="1">
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<c>1</c>
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</box>
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<box hibit="6" width="2" name="op2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="STRD_r_A1_off" oneofinclass="3" oneof="3" label="Offset" bitdiffs="P == 1 && W == 0">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="address-offset" value="signed-offset" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STRD" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field "Rt")"><Rt></a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred"><Rt2></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field "Rm")"><Rm></a><text>]</text></asmtemplate>
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</encoding>
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<encoding name="STRD_r_A1_post" oneofinclass="3" oneof="3" label="Post-indexed" bitdiffs="P == 0 && W == 0">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STRD" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>0</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field "Rt")"><Rt></a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred"><Rt2></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<encoding name="STRD_r_A1_pre" oneofinclass="3" oneof="3" label="Pre-indexed" bitdiffs="P == 1 && W == 1">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STRD" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>1</c>
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</box>
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<asmtemplate><text>STRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field "Rt")"><Rt></a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred"><Rt2></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field "Rm")"><Rm></a><text>]!</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/STRD_r/A1_A.txt" mylink="aarch32.instrs.STRD_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rt<0> == '1' then UNPREDICTABLE;
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t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); t2 = t+1; n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
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if P == '0' && W == '1' then UNPREDICTABLE;
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if t2 == 15 || m == 15 then UNPREDICTABLE;
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if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">t == 15 || t2 == 15</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">wback && (n == t || n == t2)</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_STUNKNOWN" />
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">wback && n == 15</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_WBSUPPRESS" />
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<cu_type>
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<cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">Rt<0> == '1'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_ADDITIONAL_DECODE">
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<cu_type_variable name="pseudocode" value="t<0> = '0'" />
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</cu_type>
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<cu_type constraint="Constraint_ADDITIONAL_DECODE">
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<cu_type_variable name="pseudocode" value="t2 = t" />
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</cu_type>
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<cu_type>
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<cu_type_text>The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.</cu_type_text>
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">P == '0' && W == '1'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_ADDITIONAL_DECODE">
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<cu_type_variable name="pseudocode" value="P = '1'; W = '0'" />
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</cu_type>
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<cu_type constraint="Constraint_ADDITIONAL_DECODE">
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<cu_type_variable name="pseudocode" value="P = '1'; W = '1'" />
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</cu_type>
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<cu_type constraint="Constraint_ADDITIONAL_DECODE">
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<cu_type_variable name="pseudocode" value="P = '0'; W = '0'" />
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="STRD_r_A1_off" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STRD_r_A1_off" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STRD_r_A1_off" symboldefcount="1">
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<symbol link="sa_rt"><Rt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STRD_r_A1_off" symboldefcount="1">
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<symbol link="sa_rt2"><Rt2></symbol>
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<account encodedin="">
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<intro>
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<para>Is the second general-purpose register to be transferred. This register must be <syntax><R(t+1)></syntax>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STRD_r_A1_off" symboldefcount="1">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STRD_r_A1_off" symboldefcount="1">
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<symbol link="sa__plusminus_">+/-</symbol>
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<definition encodedin="U">
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<intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">U</entry>
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<entry class="symbol">+/-</entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">-</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">+</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="STRD_r_A1_off" symboldefcount="1">
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<symbol link="sa_rm"><Rm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the general-purpose index register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/STRD_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m]);
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address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
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if <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, 8) then
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bits(64) data;
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if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then
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data<63:32> = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];
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data<31:0> = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2];
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else
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data<31:0> = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];
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data<63:32> = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2];
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<a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,8] = data;
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else
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<a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t];
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<a link="impl-aarch32.MemA.write.2" file="shared_pseudocode.xml" hover="accessor: MemA[bits(32) address, integer size] = bits(8*size) value">MemA</a>[address+4,4] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t2];
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if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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