581 lines
33 KiB
XML
581 lines
33 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="STRB_i" title="STRB (immediate) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="STRB" />
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</docvars>
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<heading>STRB (immediate)</heading>
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<desc>
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<brief>
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<para>Store Register Byte (immediate)</para>
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</brief>
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<authored>
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<para>Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="4">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>, </txt>
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<a href="#iclass_t2">T2</a>
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<txt> and </txt>
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<a href="#iclass_t3">T3</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="4" id="iclass_a1" no_encodings="3" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STRB" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/STRB_i/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1">
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<c></c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="o2" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="o1" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="STRB_i_A1_off" oneofinclass="3" oneof="8" label="Offset" bitdiffs="P == 1 && W == 0">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="address-offset" value="signed-offset" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STRB" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_3" hover="12-bit unsigned immediate byte offset [0-4095] (field "imm12")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="STRB_i_A1_post" oneofinclass="3" oneof="8" label="Post-indexed" bitdiffs="P == 0 && W == 0">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STRB" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>0</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field "Rn")"><Rn></a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_3" hover="12-bit unsigned immediate byte offset [0-4095] (field "imm12")"><imm></a></asmtemplate>
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</encoding>
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<encoding name="STRB_i_A1_pre" oneofinclass="3" oneof="8" label="Pre-indexed" bitdiffs="P == 1 && W == 1">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STRB" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>1</c>
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</box>
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<asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field "Rn")"><Rn></a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_3" hover="12-bit unsigned immediate byte offset [0-4095] (field "imm12")"><imm></a><text>]!</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/STRB_i/A1_A.txt" mylink="aarch32.instrs.STRB_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '0' && W == '1' then SEE "STRBT";
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t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);
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index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
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if t == 15 then UNPREDICTABLE;
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if wback && (n == 15 || n == t) then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">t == 15</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">wback && n == t</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_STUNKNOWN" />
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">wback && n == 15</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_WBSUPPRESS" />
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<cu_type>
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<cu_type_text>The instruction uses the addressing mode described in the equivalent immediate offset instruction.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STRB" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16" psname="aarch32/instrs/STRB_i/T1_A.txt">
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<box hibit="31" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="28" name="B" settings="1">
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<c>1</c>
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</box>
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<box hibit="27" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="26" width="5" name="imm5" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="21" width="3" name="Rn" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="18" width="3" name="Rt" usename="1">
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<c colspan="3"></c>
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</box>
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</regdiagram>
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<encoding name="STRB_i_T1" oneofinclass="1" oneof="8" label="T1">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STRB" />
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</docvars>
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<asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 5-bit unsigned immediate byte offset [0-31], default 0 (field "imm5")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/STRB_i/T1_A.txt" mylink="aarch32.instrs.STRB_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm5, 32);
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index = TRUE; add = TRUE; wback = FALSE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STRB" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/STRB_i/T2_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" width="2" name="size" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="STRB_i_T2" oneofinclass="1" oneof="8" label="T2">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T2" />
|
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STRB" />
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</docvars>
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<asmtemplate comment="<Rt>, <Rn>, <imm> can be represented in T1"><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field "imm12")"><imm></a><text>}</text><text>]</text></asmtemplate>
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<asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm_1" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field "imm12")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/STRB_i/T2_A.txt" mylink="aarch32.instrs.STRB_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rn == '1111' then UNDEFINED;
|
|
t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);
|
|
index = TRUE; add = TRUE; wback = FALSE;
|
|
if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
|
|
<constrained_unpredictables encoding="T2" ps_block="Decode">
|
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<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">t == 15</pstext>
|
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</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
<cu_type>
|
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<cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
|
|
</iclass>
|
|
<iclass name="T3" oneof="4" id="iclass_t3" no_encodings="3" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="STRB" />
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</docvars>
|
|
<iclassintro count="3"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/STRB_i/T3_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
|
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<c>1</c>
|
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<c>1</c>
|
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<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" width="2" name="size" settings="2">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" name="L" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
|
|
<c colspan="4">!= 1111</c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Rt" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" settings="1">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="10" name="P" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="9" name="U" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="8" name="W" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="7" width="8" name="imm8" usename="1">
|
|
<c colspan="8"></c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="STRB_i_T3_offn" oneofinclass="3" oneof="8" label="Offset" bitdiffs="P == 1 && U == 0 && W == 0">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="STRB" />
|
|
</docvars>
|
|
<box hibit="10" width="1" name="P">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="9" width="1" name="U">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="1" name="W">
|
|
<c>0</c>
|
|
</box>
|
|
<asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
|
|
</encoding>
|
|
<encoding name="STRB_i_T3_post" oneofinclass="3" oneof="8" label="Post-indexed" bitdiffs="P == 0 && W == 1">
|
|
<docvars>
|
|
<docvar key="address-form" value="post-indexed" />
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="STRB" />
|
|
</docvars>
|
|
<box hibit="10" width="1" name="P">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" width="1" name="W">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field "imm8")"><imm></a></asmtemplate>
|
|
</encoding>
|
|
<encoding name="STRB_i_T3_pre" oneofinclass="3" oneof="8" label="Pre-indexed" bitdiffs="P == 1 && W == 1">
|
|
<docvars>
|
|
<docvar key="address-form" value="pre-indexed" />
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="STRB" />
|
|
</docvars>
|
|
<box hibit="10" width="1" name="P">
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="8" width="1" name="W">
|
|
<c>1</c>
|
|
</box>
|
|
<asmtemplate><text>STRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_2" hover="8-bit unsigned immediate byte offset [0-255] (field "imm8")"><imm></a><text>]!</text></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/STRB_i/T3_A.txt" mylink="aarch32.instrs.STRB_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '1' && U == '1' && W == '0' then SEE "STRBT";
|
|
if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
|
|
t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32);
|
|
index = (P == '1'); add = (U == '1'); wback = (W == '1');
|
|
if t == 15 || (wback && n == t) then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<constrained_unpredictables encoding="T3" ps_block="Decode">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">t == 15</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
<cu_type>
|
|
<cu_type_text>The store instruction performs the store using the specified addressing mode but the value corresponding to R15 is <arm-defined-word>unknown</arm-defined-word>.</cu_type_text>
|
|
</cu_type>
|
|
</cu_case>
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">wback && n == t</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
<cu_type constraint="Constraint_STUNKNOWN" />
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="STRB_i_A1_off, STRB_i_T1, STRB_i_T2, STRB_i_T3_pre" symboldefcount="1">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STRB_i_A1_off, STRB_i_T1, STRB_i_T2, STRB_i_T3_pre" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STRB_i_A1_off, STRB_i_T1, STRB_i_T2, STRB_i_T3_pre" symboldefcount="1">
|
|
<symbol link="sa_rt"><Rt></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STRB_i_A1_off" symboldefcount="1">
|
|
<symbol link="sa_rn_1"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="address-offset" value="signed-offset" />
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant, but this is deprecated.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STRB_i_T1, STRB_i_T2, STRB_i_T3_pre" symboldefcount="2">
|
|
<symbol link="sa_rn"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<docvars>
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1, T2 and T3: is the general-purpose base register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STRB_i_A1_off, STRB_i_T3_pre" symboldefcount="1">
|
|
<symbol link="sa__plusminus_">+/-</symbol>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="STRB_i_T1, STRB_i_T2" symboldefcount="1">
|
|
<symbol link="sa__plus_">+</symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Specifies the offset is added to the base register.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STRB_i_A1_off" symboldefcount="1">
|
|
<symbol link="sa_imm_3"><imm></symbol>
|
|
<account encodedin="imm12">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="address-offset" value="signed-offset" />
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STRB_i_T1" symboldefcount="2">
|
|
<symbol link="sa_imm"><imm></symbol>
|
|
<account encodedin="imm5">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1: is an optional 5-bit unsigned immediate byte offset, in the range 0 to 31, defaulting to 0 and encoded in the "imm5" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STRB_i_T2" symboldefcount="3">
|
|
<symbol link="sa_imm_1"><imm></symbol>
|
|
<account encodedin="imm12">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T2: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STRB_i_T3_pre" symboldefcount="4">
|
|
<symbol link="sa_imm_2"><imm></symbol>
|
|
<account encodedin="imm8">
|
|
<docvars>
|
|
<docvar key="address-form" value="pre-indexed" />
|
|
<docvar key="armarmheading" value="T3" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T3: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/STRB_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() == <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a> then
|
|
if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);
|
|
address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
|
|
<a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,1] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]<7:0>;
|
|
if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;
|
|
else
|
|
if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);
|
|
address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
|
|
<a link="impl-aarch32.MemU.write.2" file="shared_pseudocode.xml" hover="accessor: MemU[bits(32) address, integer size] = bits(8*size) value">MemU</a>[address,1] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]<7:0>;
|
|
if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|