298 lines
15 KiB
XML
298 lines
15 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="STLEXH" title="STLEXH -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="STLEXH" />
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</docvars>
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<heading>STLEXH</heading>
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<desc>
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<brief>
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<para>Store-Release Exclusive Halfword</para>
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</brief>
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<authored>
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<para>Store-Release Exclusive Halfword stores a halfword from a register to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.</para>
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<para>The instruction also has memory ordering semantics as described in <xref linkend="AA32CHDBDIDF">Load-Acquire, Store-Release</xref>.</para>
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<para>For more information about support for shared memory see <xref linkend="CEGDAEAG">Synchronization and semaphores</xref>. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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<syntaxnotes>
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<para>Aborts and alignment</para>
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<para>If a synchronous Data Abort exception is generated by the execution of this instruction:</para>
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<list type="unordered">
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<listitem><content>Memory is not updated</content></listitem>
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<listitem><content><syntax><Rd></syntax> is not updated.</content></listitem>
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</list>
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<para>A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:</para>
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<list type="unordered">
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<listitem><content>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>TRUE</enumvalue>, the exception is generated.</content></listitem>
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<listitem><content>Otherwise, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</content></listitem>
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</list>
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<para>If <function>AArch32.ExclusiveMonitorsPass()</function> returns <enumvalue>FALSE</enumvalue> and the memory address, if accessed, would generate a synchronous Data Abort exception, it is <arm-defined-word>implementation defined</arm-defined-word> whether the exception is generated.</para>
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</syntaxnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STLEXH" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/STLEXH/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" width="2" name="size" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="10" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="9" name="ex" settings="1">
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<c>1</c>
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</box>
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<box hibit="8" name="ord" settings="1">
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<c>0</c>
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</box>
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<box hibit="7" width="4" settings="4">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="STLEXH_A1" oneofinclass="1" oneof="2" label="A1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STLEXH" />
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</docvars>
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<asmtemplate><text>STLEXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field "Rd")"><Rd></a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/STLEXH/A1_A.txt" mylink="aarch32.instrs.STLEXH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
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if d == n || d == t then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">d == t</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_STUNKNOWN" />
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">d == n</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STLEXH" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/STLEXH/T1_A.txt">
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<box hibit="31" width="11" settings="11">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="Rt2" settings="4">
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<c>(1)</c>
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<c>(1)</c>
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<c>(1)</c>
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<c>(1)</c>
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</box>
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<box hibit="7" settings="1">
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<c>1</c>
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</box>
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<box hibit="6" name="op" settings="1">
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<c>1</c>
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</box>
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<box hibit="5" width="2" name="sz" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="STLEXH_T1" oneofinclass="1" oneof="2" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STLEXH" />
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</docvars>
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<asmtemplate><text>STLEXH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="Destination general-purpose register into which the status result of store exclusive is written (field "Rd")"><Rd></a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/STLEXH/T1_A.txt" mylink="aarch32.instrs.STLEXH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
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if d == n || d == t then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="T1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">d == t</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_STUNKNOWN" />
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">d == n</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction performs the store to an <arm-defined-word>unknown</arm-defined-word> address.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
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<symbol link="sa_rd"><Rd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:</para>
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<list type="param">
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<listitem>
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<param>0</param><content>If the operation updates memory.</content>
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</listitem>
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<listitem>
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<param>1</param><content>If the operation fails to update memory.</content>
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</listitem>
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</list>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
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<symbol link="sa_rt"><Rt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="STLEXH_A1, STLEXH_T1" symboldefcount="1">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the general-purpose base register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/STLEXH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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address = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
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if <a link="AArch32.ExclusiveMonitorsPass.2" file="shared_pseudocode.xml" hover="function: boolean AArch32.ExclusiveMonitorsPass(bits(32) address, integer size)">AArch32.ExclusiveMonitorsPass</a>(address,2) then
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<a link="impl-aarch32.MemO.write.2" file="shared_pseudocode.xml" hover="accessor: MemO[bits(32) address, integer size] = bits(8*size) value">MemO</a>[address, 2] = <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[t]<15:0>;
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', 32);
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else
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('1', 32);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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