422 lines
24 KiB
XML
422 lines
24 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="STC" title="STC -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="STC" />
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</docvars>
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<heading>STC</heading>
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<desc>
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<brief>
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<para>Store data to System register</para>
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</brief>
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<authored>
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<para>Store data to System register calculates an address from a base register value and an immediate offset, and stores a word from the <xref linkend="AArch32.dbgdtrrxint">DBGDTRRXint</xref> System register to memory. It can use offset, post-indexed, pre-indexed, or unindexed addressing. For information about memory accesses, see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
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<para>In an implementation that includes EL2, the permitted <instruction>STC</instruction> access to <xref linkend="AArch32.dbgdtrrxint">DBGDTRRXint</xref> can be trapped to Hyp mode, meaning that an attempt to execute an <instruction>STC</instruction> instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see <xref linkend="BEICAABI">Trapping general Non-secure System register accesses to debug registers</xref>.</para>
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<para>For simplicity, the <instruction>STC</instruction> pseudocode does not show this possible trap to Hyp mode.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="4" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STC" />
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</docvars>
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<iclassintro count="4"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/STC/T1A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1">
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<c></c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="D" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="CRd" settings="4">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="11" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="8" name="cp15" settings="1">
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<c>0</c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="STC_A1_off" oneofinclass="4" oneof="8" label="Offset" bitdiffs="P == 1 && W == 0">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="address-offset" value="signed-offset" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STC" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> p14, c5, [</text><a link="sa_rn_1" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="STC_A1_post" oneofinclass="4" oneof="8" label="Post-indexed" bitdiffs="P == 0 && W == 1">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STC" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>0</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>1</c>
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</box>
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<asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field "imm8")"><imm></a></asmtemplate>
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</encoding>
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<encoding name="STC_A1_pre" oneofinclass="4" oneof="8" label="Pre-indexed" bitdiffs="P == 1 && W == 1">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STC" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>1</c>
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</box>
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<asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field "imm8")"><imm></a><text>]!</text></asmtemplate>
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</encoding>
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<encoding name="STC_A1_unind" oneofinclass="4" oneof="8" label="Unindexed" bitdiffs="P == 0 && U == 1 && W == 0">
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<docvars>
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<docvar key="address-form" value="unindexed" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STC" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>0</c>
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</box>
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<box hibit="23" width="1" name="U">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> p14, c5, [</text><a link="sa_rn_1" hover="General-purpose base register (field "Rn")"><Rn></a><text>], </text><a link="sa_option" hover="8-bit immediate [0-255 enclosed in { }] (field "imm8")"><option></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/STC/T1A1_A.txt" mylink="aarch32.instrs.STC.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '0' && U == '0' && W == '0' then UNDEFINED;
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n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); cp = 14;
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imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32); index = (P == '1'); add = (U == '1'); wback = (W == '1');
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if n == 15 && (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">n == 15 && wback</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_WBSUPPRESS" />
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<cu_type>
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<cu_type_text>The instruction executes with writeback to the PC. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="4" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STC" />
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</docvars>
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<iclassintro count="4"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/STC/T1A1_A.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1">
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<c></c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="D" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="CRd" settings="4">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="11" width="3" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="8" name="cp15" settings="1">
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<c>0</c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="STC_T1_off" oneofinclass="4" oneof="8" label="Offset" bitdiffs="P == 1 && W == 0">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="address-offset" value="signed-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STC" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="STC_T1_post" oneofinclass="4" oneof="8" label="Post-indexed" bitdiffs="P == 0 && W == 1">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STC" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>0</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>1</c>
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</box>
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<asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>], #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field "imm8")"><imm></a></asmtemplate>
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</encoding>
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<encoding name="STC_T1_pre" oneofinclass="4" oneof="8" label="Pre-indexed" bitdiffs="P == 1 && W == 1">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STC" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>1</c>
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</box>
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<asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="Immediate offset used for forming the address (field "imm8")"><imm></a><text>]!</text></asmtemplate>
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</encoding>
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<encoding name="STC_T1_unind" oneofinclass="4" oneof="8" label="Unindexed" bitdiffs="P == 0 && U == 1 && W == 0">
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<docvars>
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<docvar key="address-form" value="unindexed" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STC" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>0</c>
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</box>
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<box hibit="23" width="1" name="U">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>STC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> p14, c5, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>], </text><a link="sa_option" hover="8-bit immediate [0-255 enclosed in { }] (field "imm8")"><option></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/STC/T1A1_A.txt" mylink="aarch32.instrs.STC.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '0' && U == '0' && W == '0' then UNDEFINED;
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n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); cp = 14;
|
|
imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32); index = (P == '1'); add = (U == '1'); wback = (W == '1');
|
|
if n == 15 && (wback || <a link="impl-shared.CurrentInstrSet.0" file="shared_pseudocode.xml" hover="function: InstrSet CurrentInstrSet()">CurrentInstrSet</a>() != <a link="InstrSet_A32" file="shared_pseudocode.xml" hover="enumeration InstrSet {InstrSet_A64, InstrSet_A32, InstrSet_T32}">InstrSet_A32</a>) then UNPREDICTABLE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<constrained_unpredictables encoding="T1" ps_block="Decode">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">n == 15</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
<cu_type constraint="Constraint_WBSUPPRESS" />
|
|
<cu_type>
|
|
<cu_type_text>The instruction executes with writeback to the PC. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
|
|
</cu_type>
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="STC_A1_off, STC_T1_off" symboldefcount="1">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STC_A1_off, STC_T1_off" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STC_A1_off, STC_A1_unind" symboldefcount="1">
|
|
<symbol link="sa_rn_1"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For the offset or unindexed variant: is the general-purpose base register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STC_A1_pre, STC_A1_post, STC_T1_off" symboldefcount="2">
|
|
<symbol link="sa_rn"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>For the offset, post-indexed or pre-indexed variant: is the general-purpose base register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STC_A1_unind, STC_T1_unind" symboldefcount="1">
|
|
<symbol link="sa_option"><option></symbol>
|
|
<account encodedin="imm8">
|
|
<intro>
|
|
<para>Is an 8-bit immediate, in the range 0 to 255 enclosed in { }, encoded in the "imm8" field. The value of this field is ignored when executing this instruction.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="STC_A1_off, STC_T1_off" symboldefcount="1">
|
|
<symbol link="sa__plusminus_">+/-</symbol>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="STC_A1_off, STC_T1_off" symboldefcount="1">
|
|
<symbol link="sa_imm"><imm></symbol>
|
|
<account encodedin="imm8">
|
|
<intro>
|
|
<para>Is the immediate offset used for forming the address, a multiple of 4 in the range 0-1020, defaulting to 0 and encoded in the "imm8" field, as <imm>/4.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/STC/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);
|
|
address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
|
|
|
|
// System register read from DBGDTRRXint.
|
|
<a link="AArch32.SysRegRead.3" file="shared_pseudocode.xml" hover="function: AArch32.SysRegRead(integer cp_num, bits(32) instr, integer t)">AArch32.SysRegRead</a>(cp, <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), address<31:0>);
|
|
if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|