290 lines
18 KiB
XML
290 lines
18 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="RSC_r" title="RSC, RSCS (register) -- AArch32" type="instruction">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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</docvars>
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<heading>RSC, RSCS (register)</heading>
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<desc>
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<brief>
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<para>Reverse Subtract with Carry (register)</para>
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</brief>
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<authored>
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<para>Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register.</para>
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<para>If the destination register is not the PC, the RSCS variant of the instruction updates the condition flags based on the result.</para>
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<para>The field descriptions for <syntax><Rd></syntax> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:</para>
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<list type="unordered">
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<listitem><content>The RSC variant of the instruction is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
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<listitem><content>The RSCS variant of the instruction performs an exception return without the use of the stack. In this case:<list type="unordered"><listitem><content>The PE branches to the address written to the PC, and restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_<current_mode>.</content></listitem><listitem><content>The PE checks SPSR_<current_mode> for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</content></listitem><listitem><content>The instruction is <arm-defined-word>undefined</arm-defined-word> in Hyp mode.</content></listitem><listitem><content>The instruction is <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode and System mode.</content></listitem></list></content></listitem>
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</list>
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</authored>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1 and this instruction does not use R15 as either its source or destination:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="A1" oneof="1" id="iclass_a1" no_encodings="4" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="4"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/RSC_r/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="4" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" width="3" name="opc" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="20" name="S" usename="1">
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<c></c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="5" name="imm5" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="6" width="2" name="stype" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="4" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="RSC_r_A1_RRX" oneofinclass="4" oneof="4" label="RSC, rotate right with extend" bitdiffs="S == 0 && imm5 == 00000 && stype == 11">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="RSC" />
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<docvar key="mnemonic-shift-type" value="RSC-rrx" />
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<docvar key="shift-type" value="rrx" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>0</c>
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</box>
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<box hibit="11" width="5" name="imm5">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="6" width="2" name="stype">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>RSC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text>, RRX</text></asmtemplate>
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</encoding>
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<encoding name="RSC_r_A1" oneofinclass="4" oneof="4" label="RSC, shift or rotate by value" bitdiffs="S == 0 && !(imm5 == 00000 && stype == 11)">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="RSC" />
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<docvar key="mnemonic-shift-type" value="RSC-shift-no-rrx" />
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<docvar key="shift-type" value="shift-no-rrx" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>0</c>
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</box>
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<box hibit="11" width="7" name="imm5:stype">
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>N</c>
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<c>N</c>
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</box>
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<asmtemplate><text>RSC</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) (field "imm5")"><amount></a><text>}</text></asmtemplate>
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</encoding>
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<encoding name="RSCS_r_A1_RRX" oneofinclass="4" oneof="4" label="RSCS, rotate right with extend" bitdiffs="S == 1 && imm5 == 00000 && stype == 11">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="RSCS" />
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<docvar key="mnemonic-shift-type" value="RSCS-rrx" />
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<docvar key="shift-type" value="rrx" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>1</c>
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</box>
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<box hibit="11" width="5" name="imm5">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="6" width="2" name="stype">
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<c>1</c>
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<c>1</c>
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</box>
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<asmtemplate><text>RSCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text>, RRX</text></asmtemplate>
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</encoding>
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<encoding name="RSCS_r_A1" oneofinclass="4" oneof="4" label="RSCS, shift or rotate by value" bitdiffs="S == 1 && !(imm5 == 00000 && stype == 11)">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="RSCS" />
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<docvar key="mnemonic-shift-type" value="RSCS-shift-no-rrx" />
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<docvar key="shift-type" value="shift-no-rrx" />
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</docvars>
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<box hibit="20" width="1" name="S">
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<c>1</c>
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</box>
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<box hibit="11" width="7" name="imm5:stype">
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>N</c>
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<c>N</c>
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</box>
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<asmtemplate><text>RSCS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, </text><a link="sa_shift" hover="Type of shift applied to second source register (field "stype") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [1-31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) (field "imm5")"><amount></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/RSC_r/A1_A.txt" mylink="aarch32.instrs.RSC_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm); setflags = (S == '1');
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(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(stype, imm5);</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="RSC_r_A1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="RSC_r_A1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="RSC_r_A1" symboldefcount="1">
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<symbol link="sa_rd"><Rd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <syntax><Rn></syntax>. Arm deprecates using the PC as the destination register, but if the PC is used:</para>
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<list type="unordered">
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<listitem><content>For the RSC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see <xref linkend="BEICJFEH">Pseudocode description of operations on the AArch32 general-purpose registers and the PC</xref>.</content></listitem>
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<listitem><content>For the RSCS variant, the instruction performs an exception return, that restores <xref linkend="BEIDIGBH">PSTATE</xref> from SPSR_<current_mode>.</content></listitem>
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</list>
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</intro>
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</account>
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</explanation>
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<explanation enclist="RSC_r_A1" symboldefcount="1">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="RSC_r_A1" symboldefcount="1">
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<symbol link="sa_rm"><Rm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="RSC_r_A1" symboldefcount="1">
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<symbol link="sa_shift"><shift></symbol>
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<definition encodedin="stype">
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<intro>Is the type of shift to be applied to the second source register, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">stype</entry>
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<entry class="symbol"><shift></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">00</entry>
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<entry class="symbol">LSL</entry>
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</row>
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<row>
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<entry class="bitfield">01</entry>
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<entry class="symbol">LSR</entry>
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</row>
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<row>
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<entry class="bitfield">10</entry>
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<entry class="symbol">ASR</entry>
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</row>
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<row>
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<entry class="bitfield">11</entry>
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<entry class="symbol">ROR</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="RSC_r_A1" symboldefcount="1">
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<symbol link="sa_amount"><amount></symbol>
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<account encodedin="imm5">
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<intro>
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<para>Is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR) encoded in the "imm5" field as <amount> modulo 32.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/RSC_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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shifted = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);
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(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(NOT(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]), shifted, PSTATE.C);
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if d == 15 then
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if setflags then
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<a link="impl-aarch32.ALUExceptionReturn.1" file="shared_pseudocode.xml" hover="function: ALUExceptionReturn(bits(32) address)">ALUExceptionReturn</a>(result);
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else
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<a link="impl-aarch32.ALUWritePC.1" file="shared_pseudocode.xml" hover="function: ALUWritePC(bits(32) address)">ALUWritePC</a>(result);
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else
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = result;
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if setflags then
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PSTATE.<N,Z,C,V> = nzcv;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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