437 lines
25 KiB
XML
437 lines
25 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="RFE" title="RFE, RFEDA, RFEDB, RFEIA, RFEIB -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="RFE" />
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</docvars>
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<heading>RFE, RFEDA, RFEDB, RFEIA, RFEIB</heading>
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<desc>
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<brief>
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<para>Return From Exception</para>
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</brief>
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<authored>
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<para>Return From Exception loads two consecutive memory locations using an address in a base register:</para>
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<list type="unordered">
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<listitem><content>The word loaded from the lower address is treated as an instruction address. The PE branches to it.</content></listitem>
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<listitem><content>The word loaded from the higher address is used to restore <xref linkend="BEIDIGBH">PSTATE</xref>. This word must be in the format of an SPSR.</content></listitem>
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</list>
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<para>An address adjusted by the size of the data loaded can optionally be written back to the base register.</para>
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<para>The PE checks the value of the word loaded from the higher address for an illegal return event. See <xref linkend="CHDDDJDB">Illegal return events from AArch32 state</xref>.</para>
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<para><instruction>RFE</instruction> is <arm-defined-word>undefined</arm-defined-word> in Hyp mode and <arm-defined-word>constrained unpredictable</arm-defined-word> in User mode.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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<syntaxnotes>
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<para><instruction>RFEFA</instruction>, <instruction>RFEEA</instruction>, <instruction>RFEFD</instruction>, and <instruction>RFEED</instruction> are pseudo-instructions for <instruction>RFEDA</instruction>, <instruction>RFEDB</instruction>, <instruction>RFEIA</instruction>, and <instruction>RFEIB</instruction> respectively, referring to their use for popping data from Full Ascending, Empty Ascending, Full Descending, and Empty Descending stacks.</para>
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</syntaxnotes>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t2">T2</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="3" id="iclass_a1" no_encodings="4" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="RFE" />
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</docvars>
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<iclassintro count="4"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/RFE/A1_AS.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1">
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<c></c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="S" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="11" name="op" settings="11">
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(1)</c>
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<c>(0)</c>
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<c>(1)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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</box>
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<box hibit="4" width="5" name="mode" settings="5">
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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</box>
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</regdiagram>
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<encoding name="RFEDA_A1_AS" oneofinclass="4" oneof="6" label="Decrement After" bitdiffs="P == 0 && U == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="ldmstm-mode" value="dec-after" />
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<docvar key="mnemonic" value="RFE" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>0</c>
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</box>
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<box hibit="23" width="1" name="U">
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<c>0</c>
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</box>
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<asmtemplate comment="Preferred syntax"><text>RFEDA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
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<asmtemplate comment="Alternate syntax, Full Ascending stack"><text>RFEFA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
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</encoding>
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<encoding name="RFEDB_A1_AS" oneofinclass="4" oneof="6" label="Decrement Before" bitdiffs="P == 1 && U == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="ldmstm-mode" value="dec-before" />
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<docvar key="mnemonic" value="RFE" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="23" width="1" name="U">
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<c>0</c>
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</box>
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<asmtemplate comment="Preferred syntax"><text>RFEDB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
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<asmtemplate comment="Alternate syntax, Empty Ascending stack"><text>RFEEA</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
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</encoding>
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<encoding name="RFEIA_A1_AS" oneofinclass="4" oneof="6" label="Increment After" bitdiffs="P == 0 && U == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="ldmstm-mode" value="inc-after" />
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<docvar key="mnemonic" value="RFE" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>0</c>
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</box>
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<box hibit="23" width="1" name="U">
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<c>1</c>
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</box>
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<asmtemplate comment="Preferred syntax"><text>RFE</text><a link="sa_ia_1" hover="Optional suffix to indicate the Increment After variant">{IA}</a><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
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<asmtemplate comment="Alternate syntax, Full Descending stack"><text>RFEFD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
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</encoding>
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<encoding name="RFEIB_A1_AS" oneofinclass="4" oneof="6" label="Increment Before" bitdiffs="P == 1 && U == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="ldmstm-mode" value="inc-before" />
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<docvar key="mnemonic" value="RFE" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="23" width="1" name="U">
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<c>1</c>
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</box>
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<asmtemplate comment="Preferred syntax"><text>RFEIB</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
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<asmtemplate comment="Alternate syntax, Empty Descending stack"><text>RFEED</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/RFE/A1_AS.txt" mylink="aarch32.instrs.RFE.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
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wback = (W == '1'); increment = (U == '1'); wordhigher = (P == U);
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if n == 15 then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="ldmstm-mode" value="dec-before" />
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<docvar key="mnemonic" value="RFE" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/RFE/T1_AS.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="24" width="2" name="opc" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="22" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" name="P" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="14" name="M" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="13" width="14" name="register_list" settings="14">
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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</box>
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</regdiagram>
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<encoding name="RFE_T1_AS" oneofinclass="1" oneof="6" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="ldmstm-mode" value="dec-before" />
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<docvar key="mnemonic" value="RFE" />
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</docvars>
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<asmtemplate comment="Outside or last in IT block, preferred syntax"><text>RFEDB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
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<asmtemplate comment="Outside or last in IT block, alternate syntax, Full Ascending stack"><text>RFEFA</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/RFE/T1_AS.txt" mylink="aarch32.instrs.RFE.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); wback = (W == '1'); increment = FALSE; wordhigher = FALSE;
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if n == 15 then UNPREDICTABLE;
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if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() && !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="ldmstm-mode" value="inc-after" />
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<docvar key="mnemonic" value="RFE" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/RFE/T2_AS.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="24" width="2" name="opc" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" name="P" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="14" name="M" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="13" width="14" name="register_list" settings="14">
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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</box>
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</regdiagram>
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<encoding name="RFE_T2_AS" oneofinclass="1" oneof="6" label="T2">
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<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="ldmstm-mode" value="inc-after" />
|
|
<docvar key="mnemonic" value="RFE" />
|
|
</docvars>
|
|
<asmtemplate comment="Outside or last in IT block, preferred syntax"><text>RFE</text><a link="sa_ia" hover="Optional suffix for Increment After form">{IA}</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
|
|
<asmtemplate comment="Outside or last in IT block, alternate syntax, Full Descending stack"><text>RFEFD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><a link="sa_0d33" hover="The address adjusted by the size of data loaded is written back to the base register (field "W")">{!}</a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/RFE/T2_AS.txt" mylink="aarch32.instrs.RFE.T2_AS.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); wback = (W == '1'); increment = TRUE; wordhigher = FALSE;
|
|
if n == 15 then UNPREDICTABLE;
|
|
if <a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>() && !<a link="impl-aarch32.LastInITBlock.0" file="shared_pseudocode.xml" hover="function: boolean LastInITBlock()">LastInITBlock</a>() then UNPREDICTABLE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="RFEIA_A1_AS" symboldefcount="1">
|
|
<symbol link="sa_ia_1">IA</symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is an optional suffix to indicate the Increment After variant.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="RFE_T2_AS" symboldefcount="2">
|
|
<symbol link="sa_ia">IA</symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T2: is an optional suffix for the Increment After form.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="RFEDA_A1_AS" symboldefcount="1">
|
|
<symbol link="sa_c_1"><c></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="ldmstm-mode" value="dec-after" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. <syntax><c></syntax> must be <value>AL</value> or omitted.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="RFE_T1_AS, RFE_T2_AS" symboldefcount="2">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<docvars>
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="RFEDA_A1_AS, RFE_T1_AS, RFE_T2_AS" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="RFEDA_A1_AS, RFE_T1_AS, RFE_T2_AS" symboldefcount="1">
|
|
<symbol link="sa_rn"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<intro>
|
|
<para>Is the general-purpose base register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="RFEDA_A1_AS, RFE_T1_AS, RFE_T2_AS" symboldefcount="1">
|
|
<symbol link="sa_0d33">!</symbol>
|
|
<account encodedin="W">
|
|
<intro>
|
|
<para>The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/RFE/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
if PSTATE.EL == <a link="EL2" file="shared_pseudocode.xml" hover="constant bits(2) EL2 = '10'">EL2</a> then
|
|
UNDEFINED;
|
|
elsif PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then
|
|
UNPREDICTABLE; // UNDEFINED or NOP
|
|
else
|
|
address = if increment then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-8;
|
|
if wordhigher then address = address+4;
|
|
new_pc_value = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];
|
|
spsr = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];
|
|
if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = if increment then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]+8 else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]-8;
|
|
<a link="AArch32.ExceptionReturn.2" file="shared_pseudocode.xml" hover="function: AArch32.ExceptionReturn(bits(32) new_pc_in, bits(32) spsr)">AArch32.ExceptionReturn</a>(new_pc_value, spsr);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<constrained_unpredictables ps_block="Operation">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">PSTATE.EL == EL0</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</instructionsection>
|