198 lines
10 KiB
XML
198 lines
10 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="PUSH_STMDB" title="PUSH (multiple registers) -- AArch32" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="PUSH" />
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="STM" />
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</docvars>
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<heading>PUSH (multiple registers)</heading>
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<desc>
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<brief>Push multiple registers to Stack</brief>
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<longer> stores multiple general-purpose registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data</longer>
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</desc>
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<aliasto refiform="stmdb.xml" iformid="STMDB">STMDB, STMFD</aliasto>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STM" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" settings="1">
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<c>1</c>
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</box>
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<box hibit="23" name="U" settings="1">
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<c>0</c>
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</box>
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<box hibit="22" name="op" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1" settings="1" psbits="1">
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<c>1</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" width="16" name="register_list" usename="1">
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<c colspan="16"></c>
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</box>
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</regdiagram>
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<encoding name="PUSH_STMDB_A1" oneofinclass="1" oneof="2" label="A1">
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<docvars>
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<docvar key="alias_mnemonic" value="PUSH" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="STM" />
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</docvars>
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<asmtemplate><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_registers_3" hover="List of two or more registers to be stored"><registers></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="stmdb.xml#STMDB_A1">STMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> SP!, </text><a link="sa_registers_3" hover="List of two or more registers to be stored"><registers></a></asmtemplate>
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<aliascond><a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(register_list) > 1</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STM" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="24" width="2" name="opc" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1" settings="1" psbits="1">
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<c>1</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="15" name="P" usename="1" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="14" name="M" usename="1">
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<c></c>
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</box>
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<box hibit="13" width="14" name="register_list" usename="1">
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<c colspan="14"></c>
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</box>
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</regdiagram>
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<encoding name="PUSH_STMDB_T1" oneofinclass="1" oneof="2" label="T1">
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<docvars>
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<docvar key="alias_mnemonic" value="PUSH" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="STM" />
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</docvars>
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<asmtemplate comment="All registers in R0-R7, LR"><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>.W </text><a link="sa_registers_2" hover="List of one or more registers to be stored (field "register_list")"><registers></a></asmtemplate>
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<asmtemplate><text>PUSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_registers_2" hover="List of one or more registers to be stored (field "register_list")"><registers></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="stmdb.xml#STMDB_T1">STMDB</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> SP!, </text><a link="sa_registers_2" hover="List of one or more registers to be stored (field "register_list")"><registers></a></asmtemplate>
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<aliascond><a link="impl-shared.BitCount.1" file="shared_pseudocode.xml" hover="function: integer BitCount(bits(N) x)">BitCount</a>(M:register_list) > 1</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="PUSH_STMDB_A1, PUSH_STMDB_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PUSH_STMDB_A1, PUSH_STMDB_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PUSH_STMDB_A1" symboldefcount="1">
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<symbol link="sa_registers_3"><registers></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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</docvars>
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<intro>
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<para>For encoding A1: is a list of two or more registers to be stored, separated by commas and surrounded by { and }. The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
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<para>The SP and PC can be in the list. However:</para>
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<list type="unordered">
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<listitem><content>Arm deprecates the use of instructions that include the PC in the list.</content></listitem>
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<listitem><content>If the SP is in the list, and it is not the lowest-numbered register in the list, the instruction stores an <arm-defined-word>unknown</arm-defined-word> value for the SP.</content></listitem>
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</list>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PUSH_STMDB_T1" symboldefcount="2">
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<symbol link="sa_registers_2"><registers></symbol>
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<account encodedin="register_list">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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</docvars>
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<intro>
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<para>For encoding T1: is a list of one or more registers to be stored, separated by commas and surrounded by { and }. The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to the highest memory address. See also <xref linkend="CHDDBEDG">Encoding of lists of general-purpose registers and the PC</xref>.</para>
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<para>The registers in the list must be in the range R0-R12, encoded in the "register_list" field, and can optionally contain the LR. If the LR is in the list, the "M" field is set to 1, otherwise it defaults to 0.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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</instructionsection>
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