442 lines
23 KiB
XML
442 lines
23 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="PLI_i" title="PLI (immediate, literal) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="PLI" />
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</docvars>
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<heading>PLI (immediate, literal)</heading>
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<desc>
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<brief>
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<para>Preload Instruction (immediate, literal)</para>
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</brief>
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<authored>
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<para>Preload Instruction signals the memory system that instruction memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the instruction cache.</para>
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<para>The effect of a <instruction>PLI</instruction> instruction is <arm-defined-word>implementation defined</arm-defined-word>. For more information, see <xref linkend="CEGJJFCA">Preloading caches</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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<syntaxnotes>
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<para>For the literal forms of the instruction, encoding T3 is used, or Rn is encoded as <binarynumber>0b1111</binarynumber> in encoding A1, to indicate that the PC is the base register.</para>
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<para>The alternative literal syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
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</syntaxnotes>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="4">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>, </txt>
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<a href="#iclass_t2">T2</a>
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<txt> and </txt>
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<a href="#iclass_t3">T3</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="4" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="PLI" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/PLI_i/A1_A.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="D" settings="1">
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<c>0</c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="R" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="14" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="13" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="12" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="PLI_i_A1" oneofinclass="1" oneof="4" label="A1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="PLI" />
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</docvars>
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<asmtemplate><text>PLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_3" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field "imm12")"><imm></a><text>}</text><text>]</text></asmtemplate>
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<asmtemplate comment="Normal form"><text>PLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_label" hover="The label of instruction that is likely to be accessed in the near future"><label></a></asmtemplate>
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<asmtemplate comment="Alternative form"><text>PLI</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_3" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field "imm12")"><imm></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/PLI_i/A1_A.txt" mylink="aarch32.instrs.PLI_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32); add = (U == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="4" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PLI" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/PLI_i/T1_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" width="2" name="size" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="15" width="4" name="Rt" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="PLI_i_T1" oneofinclass="1" oneof="4" label="T1">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PLI" />
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</docvars>
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<asmtemplate><text>PLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field "imm12")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/PLI_i/T1_A.txt" mylink="aarch32.instrs.PLI_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rn == '1111' then SEE "encoding T3";
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n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32); add = TRUE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T2" oneof="4" id="iclass_t2" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PLI" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/PLI_i/T2_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" width="2" name="size" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="15" width="4" name="Rt" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="PLI_i_T2" oneofinclass="1" oneof="4" label="T2">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PLI" />
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</docvars>
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<asmtemplate><text>PLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/PLI_i/T2_A.txt" mylink="aarch32.instrs.PLI_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rn == '1111' then SEE "encoding T3";
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n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32); add = FALSE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T3" oneof="4" id="iclass_t3" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="armarmheading" value="T3" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PLI" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/PLI_i/T3_A.txt">
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<box hibit="31" width="8" settings="8">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" width="2" name="size" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" width="5" settings="5">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Rt" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="PLI_i_T3" oneofinclass="1" oneof="4" label="T3">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="armarmheading" value="T3" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PLI" />
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</docvars>
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<asmtemplate comment="Preferred syntax"><text>PLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_label" hover="The label of instruction that is likely to be accessed in the near future"><label></a></asmtemplate>
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<asmtemplate comment="Alternative syntax"><text>PLI</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_2" hover="12-bit unsigned immediate byte offset [0-4095] (field "imm12")"><imm></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/PLI_i/T3_A.txt" mylink="aarch32.instrs.PLI_i.T3_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">n = 15; imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32); add = (U == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="PLI_i_A1" symboldefcount="1">
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<symbol link="sa_c_1"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must be <value>AL</value> or omitted.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PLI_i_T1, PLI_i_T2, PLI_i_T3" symboldefcount="2">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1, T2 and T3: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PLI_i_A1, PLI_i_T1, PLI_i_T2, PLI_i_T3" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
|
||
</explanation>
|
||
<explanation enclist="PLI_i_A1, PLI_i_T3" symboldefcount="1">
|
||
<symbol link="sa_label"><label></symbol>
|
||
<account encodedin="imm12">
|
||
<intro>
|
||
<para>The label of the instruction that is likely to be accessed in the near future. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. The offset must be in the range –4095 to 4095.</para>
|
||
<para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>.</para>
|
||
<para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>.</para>
|
||
</intro>
|
||
</account>
|
||
</explanation>
|
||
<explanation enclist="PLI_i_A1, PLI_i_T1, PLI_i_T2" symboldefcount="1">
|
||
<symbol link="sa_rn"><Rn></symbol>
|
||
<account encodedin="Rn">
|
||
<intro>
|
||
<para>Is the general-purpose base register, encoded in the "Rn" field.</para>
|
||
</intro>
|
||
</account>
|
||
</explanation>
|
||
<explanation enclist="PLI_i_A1, PLI_i_T3" symboldefcount="1">
|
||
<symbol link="sa__plusminus_">+/-</symbol>
|
||
<definition encodedin="U">
|
||
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
||
<table class="valuetable">
|
||
<tgroup cols="2">
|
||
<thead>
|
||
<row>
|
||
<entry class="bitfield">U</entry>
|
||
<entry class="symbol">+/-</entry>
|
||
</row>
|
||
</thead>
|
||
<tbody>
|
||
<row>
|
||
<entry class="bitfield">0</entry>
|
||
<entry class="symbol">-</entry>
|
||
</row>
|
||
<row>
|
||
<entry class="bitfield">1</entry>
|
||
<entry class="symbol">+</entry>
|
||
</row>
|
||
</tbody>
|
||
</tgroup>
|
||
</table>
|
||
</definition>
|
||
</explanation>
|
||
<explanation enclist="PLI_i_T1" symboldefcount="1">
|
||
<symbol link="sa__plus_">+</symbol>
|
||
<account encodedin="">
|
||
<intro>
|
||
<para>Specifies the offset is added to the base register.</para>
|
||
</intro>
|
||
</account>
|
||
</explanation>
|
||
<explanation enclist="PLI_i_A1" symboldefcount="1">
|
||
<symbol link="sa_imm_3"><imm></symbol>
|
||
<account encodedin="imm12">
|
||
<docvars>
|
||
<docvar key="armarmheading" value="A1" />
|
||
<docvar key="isa" value="A32" />
|
||
</docvars>
|
||
<intro>
|
||
<para>For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
|
||
</intro>
|
||
</account>
|
||
</explanation>
|
||
<explanation enclist="PLI_i_T1" symboldefcount="2">
|
||
<symbol link="sa_imm"><imm></symbol>
|
||
<account encodedin="imm12">
|
||
<docvars>
|
||
<docvar key="address-form" value="base-plus-offset" />
|
||
<docvar key="armarmheading" value="T1" />
|
||
<docvar key="isa" value="T32" />
|
||
</docvars>
|
||
<intro>
|
||
<para>For encoding T1: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
|
||
</intro>
|
||
</account>
|
||
</explanation>
|
||
<explanation enclist="PLI_i_T2" symboldefcount="3">
|
||
<symbol link="sa_imm_1"><imm></symbol>
|
||
<account encodedin="imm8">
|
||
<docvars>
|
||
<docvar key="address-form" value="base-plus-offset" />
|
||
<docvar key="armarmheading" value="T2" />
|
||
<docvar key="isa" value="T32" />
|
||
</docvars>
|
||
<intro>
|
||
<para>For encoding T2: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
|
||
</intro>
|
||
</account>
|
||
</explanation>
|
||
<explanation enclist="PLI_i_T3" symboldefcount="4">
|
||
<symbol link="sa_imm_2"><imm></symbol>
|
||
<account encodedin="imm12">
|
||
<docvars>
|
||
<docvar key="address-form" value="literal" />
|
||
<docvar key="armarmheading" value="T3" />
|
||
<docvar key="isa" value="T32" />
|
||
</docvars>
|
||
<intro>
|
||
<para>For encoding T3: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.</para>
|
||
</intro>
|
||
</account>
|
||
</explanation>
|
||
</explanations>
|
||
<ps_section howmany="1">
|
||
<ps name="aarch32/instrs/PLI_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
||
EncodingSpecificOperations();
|
||
base = if n == 15 then <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
|
||
address = if add then (base + imm32) else (base - imm32);
|
||
<a link="impl-aarch32.Hint_PreloadInstr.1" file="shared_pseudocode.xml" hover="function: Hint_PreloadInstr(bits(32) address)">Hint_PreloadInstr</a>(address);</pstext>
|
||
</ps>
|
||
</ps_section>
|
||
</instructionsection>
|