408 lines
21 KiB
XML
408 lines
21 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="PLD_i" title="PLD, PLDW (immediate) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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</docvars>
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<heading>PLD, PLDW (immediate)</heading>
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<desc>
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<brief>
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<para>Preload Data (immediate)</para>
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</brief>
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<authored>
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<para>Preload Data (immediate) signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into the data cache.</para>
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<para>The <instruction>PLD</instruction> instruction signals that the likely memory access is a read, and the <instruction>PLDW</instruction> instruction signals that it is a write.</para>
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<para>The effect of a <instruction>PLD</instruction> or <instruction>PLDW</instruction> instruction is <arm-defined-word>implementation defined</arm-defined-word>. For more information, see <xref linkend="CEGJJFCA">Preloading caches</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t2">T2</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="3" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/PLD_i/A1_A.txt" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="D" settings="1">
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<c>1</c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="R" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="15" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="14" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="13" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="12" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="PLD_i_A1" oneofinclass="2" oneof="6" label="Preload read" bitdiffs="R == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="PLD" />
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<docvar key="preload-type" value="pld" />
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</docvars>
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<box hibit="22" width="1" name="R">
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<c>1</c>
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</box>
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<asmtemplate><text>PLD</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_2" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field "imm12")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="PLDW_i_A1" oneofinclass="2" oneof="6" label="Preload write" bitdiffs="R == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="PLDW" />
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<docvar key="preload-type" value="pldw" />
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</docvars>
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<box hibit="22" width="1" name="R">
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<c>0</c>
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</box>
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<asmtemplate><text>PLDW</text><text>{</text><a link="sa_c_1" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_2" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field "imm12")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/PLD_i/A1_A.txt" mylink="aarch32.instrs.PLD_i.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rn == '1111' then SEE "PLD (literal)";
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n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32); add = (U == '1'); is_pldw = (R == '0');</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="3" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/PLD_i/T1_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="22" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="15" width="4" name="Rt" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="PLD_i_T1" oneofinclass="2" oneof="6" label="Preload read" bitdiffs="W == 0">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PLD" />
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<docvar key="preload-type" value="pld" />
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</docvars>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>PLD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field "imm12")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="PLDW_i_T1" oneofinclass="2" oneof="6" label="Preload write" bitdiffs="W == 1">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PLDW" />
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<docvar key="preload-type" value="pldw" />
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</docvars>
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<box hibit="21" width="1" name="W">
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<c>1</c>
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</box>
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<asmtemplate><text>PLDW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #</text><a link="sa__plus_" hover="Specifies the offset is added to the base register">{+}</a><a link="sa_imm" hover="Optional 12-bit unsigned immediate byte offset [0-4095], default 0 (field "imm12")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/PLD_i/T1_A.txt" mylink="aarch32.instrs.PLD_i.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rn == '1111' then SEE "PLD (literal)";
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n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32); add = TRUE; is_pldw = (W == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T2" oneof="3" id="iclass_t2" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/PLD_i/T2_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="22" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="15" width="4" name="Rt" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="PLD_i_T2" oneofinclass="2" oneof="6" label="Preload read" bitdiffs="W == 0">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PLD" />
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<docvar key="preload-type" value="pld" />
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</docvars>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>PLD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<encoding name="PLDW_i_T2" oneofinclass="2" oneof="6" label="Preload write" bitdiffs="W == 1">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PLDW" />
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<docvar key="preload-type" value="pldw" />
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</docvars>
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<box hibit="21" width="1" name="W">
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<c>1</c>
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</box>
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<asmtemplate><text>PLDW</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text> </text><text>{</text><text>, #-</text><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field "imm8")"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/PLD_i/T2_A.txt" mylink="aarch32.instrs.PLD_i.T2_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rn == '1111' then SEE "PLD (literal)";
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n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8, 32); add = FALSE; is_pldw = (W == '1');</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="PLD_i_A1" symboldefcount="1">
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<symbol link="sa_c_1"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>. Must be <value>AL</value> or omitted.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PLD_i_T1, PLD_i_T2" symboldefcount="2">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1 and T2: see <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PLD_i_A1, PLD_i_T1, PLD_i_T2" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PLD_i_A1, PLD_i_T1, PLD_i_T2" symboldefcount="1">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the general-purpose base register, encoded in the "Rn" field. If the PC is used, see <xref linkend="A32T32-base.instructions.PLD_l">PLD (literal)</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PLD_i_A1" symboldefcount="1">
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<symbol link="sa__plusminus_">+/-</symbol>
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<definition encodedin="U">
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|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
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|
<table class="valuetable">
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|
<tgroup cols="2">
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|
<thead>
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|
<row>
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|
<entry class="bitfield">U</entry>
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|
<entry class="symbol">+/-</entry>
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|
</row>
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|
</thead>
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|
<tbody>
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|
<row>
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|
<entry class="bitfield">0</entry>
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|
<entry class="symbol">-</entry>
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|
</row>
|
|
<row>
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|
<entry class="bitfield">1</entry>
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|
<entry class="symbol">+</entry>
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|
</row>
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|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
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|
</explanation>
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|
<explanation enclist="PLD_i_T1" symboldefcount="1">
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|
<symbol link="sa__plus_">+</symbol>
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|
<account encodedin="">
|
|
<intro>
|
|
<para>Specifies the offset is added to the base register.</para>
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|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="PLD_i_A1" symboldefcount="1">
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|
<symbol link="sa_imm_2"><imm></symbol>
|
|
<account encodedin="imm12">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="PLD_i_T1" symboldefcount="2">
|
|
<symbol link="sa_imm"><imm></symbol>
|
|
<account encodedin="imm12">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="PLD_i_T2" symboldefcount="3">
|
|
<symbol link="sa_imm_1"><imm></symbol>
|
|
<account encodedin="imm8">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="armarmheading" value="T2" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T2: is an 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm8" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/PLD_i/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
address = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + imm32) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - imm32);
|
|
if is_pldw then
|
|
<a link="impl-aarch32.Hint_PreloadDataForWrite.1" file="shared_pseudocode.xml" hover="function: Hint_PreloadDataForWrite(bits(32) address)">Hint_PreloadDataForWrite</a>(address);
|
|
else
|
|
<a link="impl-aarch32.Hint_PreloadData.1" file="shared_pseudocode.xml" hover="function: Hint_PreloadData(bits(32) address)">Hint_PreloadData</a>(address);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|