318 lines
19 KiB
XML
318 lines
19 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="PKH" title="PKHBT, PKHTB -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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</docvars>
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<heading>PKHBT, PKHTB</heading>
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<desc>
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<brief>
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<para>Pack Halfword</para>
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</brief>
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<authored>
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<para>Pack Halfword combines one halfword of its first operand with the other halfword of its shifted second operand.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, this instruction has passed its condition execution check, and does not use R15 as either its source or destination:</para>
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<list type="unordered">
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<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
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</list>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="2" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/PKH/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="8" settings="8">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="5" name="imm5" usename="1">
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<c colspan="5"></c>
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</box>
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<box hibit="6" name="tb" usename="1">
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<c></c>
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</box>
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<box hibit="5" width="2" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="PKHBT_A1" oneofinclass="2" oneof="4" label="PKHBT" bitdiffs="tb == 0">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="PKHBT" />
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</docvars>
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<box hibit="6" width="1" name="tb">
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<c>0</c>
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</box>
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<asmtemplate><text>PKHBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, LSL #</text><a link="sa_imm_1" hover="The shift to apply to the value read from {syntax{<Rm>}} (field "imm5")"><imm></a><text>}</text></asmtemplate>
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</encoding>
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<encoding name="PKHTB_A1" oneofinclass="2" oneof="4" label="PKHTB" bitdiffs="tb == 1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="PKHTB" />
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</docvars>
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<box hibit="6" width="1" name="tb">
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<c>1</c>
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</box>
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<asmtemplate><text>PKHTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, ASR #</text><a link="sa_imm_1" hover="The shift to apply to the value read from {syntax{<Rm>}} (field "imm5")"><imm></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/PKH/A1_A.txt" mylink="aarch32.instrs.PKH.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm); tbform = (tb == '1');
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(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(tb:'0', imm5);
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if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="2" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="2"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/PKH/T1_A.txt" tworows="1">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="24" width="4" name="op1" settings="4">
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="20" name="S" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="14" width="3" name="imm3" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="11" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="2" name="imm2" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="5" name="tb" usename="1">
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<c></c>
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</box>
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<box hibit="4" name="T" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="PKHBT_T1" oneofinclass="2" oneof="4" label="PKHBT" bitdiffs="tb == 0">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PKHBT" />
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</docvars>
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<box hibit="5" width="1" name="tb">
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<c>0</c>
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</box>
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<asmtemplate comment="tbform == FALSE"><text>PKHBT</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, LSL #</text><a link="sa_imm" hover="The shift to apply to the value read from {syntax{<Rm>}} (field "imm3:imm2")"><imm></a><text>}</text></asmtemplate>
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</encoding>
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<encoding name="PKHTB_T1" oneofinclass="2" oneof="4" label="PKHTB" bitdiffs="tb == 1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="PKHTB" />
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</docvars>
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<box hibit="5" width="1" name="tb">
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<c>1</c>
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</box>
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<asmtemplate comment="tbform == TRUE"><text>PKHTB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rn" hover="First general-purpose source register (field "Rn")"><Rn></a><text>, </text><a link="sa_rm" hover="Second general-purpose source register (field "Rm")"><Rm></a><text> </text><text>{</text><text>, ASR #</text><a link="sa_imm" hover="The shift to apply to the value read from {syntax{<Rm>}} (field "imm3:imm2")"><imm></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/PKH/T1_A.txt" mylink="aarch32.instrs.PKH.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if S == '1' || T == '1' then UNDEFINED;
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d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm); tbform = (tb == '1');
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(shift_t, shift_n) = <a link="impl-aarch32.DecodeImmShift.2" file="shared_pseudocode.xml" hover="function: (SRType, integer) DecodeImmShift(bits(2) srtype, bits(5) imm5)">DecodeImmShift</a>(tb:'0', imm3:imm2);
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if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="PKHBT_A1, PKHBT_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PKHBT_A1, PKHBT_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PKHBT_A1, PKHBT_T1" symboldefcount="1">
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<symbol link="sa_rd"><Rd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PKHBT_A1, PKHBT_T1" symboldefcount="1">
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<symbol link="sa_rn"><Rn></symbol>
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<account encodedin="Rn">
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<intro>
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<para>Is the first general-purpose source register, encoded in the "Rn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PKHBT_A1, PKHBT_T1" symboldefcount="1">
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<symbol link="sa_rm"><Rm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the second general-purpose source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PKHBT_A1" symboldefcount="1">
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<symbol link="sa_imm_1"><imm></symbol>
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<account encodedin="imm5">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: the shift to apply to the value read from <syntax><Rm></syntax>, encoded in the "imm5" field.</para>
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<para>For <instruction>PKHBT</instruction>, it is one of:</para>
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<list type="param">
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<listitem>
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<param>omitted</param><content>No shift, encoded as <binarynumber>0b00000</binarynumber>.</content>
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</listitem>
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<listitem>
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<param>1-31</param><content>Left shift by specified number of bits, encoded as a binary number.</content>
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</listitem>
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</list>
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<para>For <instruction>PKHTB</instruction>, it is one of:</para>
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<list type="param">
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<listitem>
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<param>omitted</param><content>Instruction is a pseudo-instruction and is assembled as though <instruction>PKHBT{<c>}{<q>} <Rd>, <Rm>, <Rn></instruction> had been written.</content>
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</listitem>
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<listitem>
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<param>1-32</param><content>Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as <binarynumber>0b00000</binarynumber>. Other shift amounts are encoded as binary numbers.</content>
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</listitem>
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</list>
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<note>
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<para>An assembler can permit <syntax><imm></syntax> = 0 to mean the same thing as omitting the shift, but this is not standard UAL and must not be used for disassembly.</para>
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</note>
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</intro>
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</account>
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</explanation>
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<explanation enclist="PKHBT_T1" symboldefcount="2">
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<symbol link="sa_imm"><imm></symbol>
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<account encodedin="imm3:imm2">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: the shift to apply to the value read from <syntax><Rm></syntax>, encoded in the "imm3:imm2" field.</para>
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<para>For <instruction>PKHBT</instruction>, it is one of:</para>
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<list type="param">
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<listitem>
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<param>omitted</param><content>No shift, encoded as <binarynumber>0b00000</binarynumber>.</content>
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</listitem>
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<listitem>
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<param>1-31</param><content>Left shift by specified number of bits, encoded as a binary number.</content>
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</listitem>
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</list>
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<para>For <instruction>PKHTB</instruction>, it is one of:</para>
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<list type="param">
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<listitem>
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<param>omitted</param><content>Instruction is a pseudo-instruction and is assembled as though <instruction>PKHBT{<c>}{<q>} <Rd>, <Rm>, <Rn></instruction> had been written.</content>
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</listitem>
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<listitem>
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<param>1-32</param><content>Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as <binarynumber>0b00000</binarynumber>. Other shift amounts are encoded as binary numbers.</content>
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</listitem>
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</list>
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<note>
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<para>An assembler can permit <syntax><imm></syntax> = 0 to mean the same thing as omitting the shift, but this is not standard UAL and must not be used for disassembly.</para>
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</note>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/PKH/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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operand2 = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C); // PSTATE.C ignored
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]<15:0> = if tbform then operand2<15:0> else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]<15:0>;
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d]<31:16> = if tbform then <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n]<31:16> else operand2<31:16>;</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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