201 lines
11 KiB
XML
201 lines
11 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="MSR_i" title="MSR (immediate) -- AArch32" type="instruction">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="MSR" />
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</docvars>
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<heading>MSR (immediate)</heading>
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<desc>
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<brief>
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<para>Move immediate value to Special register</para>
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</brief>
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<authored>
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<para>Move immediate value to Special register moves selected bits of an immediate value to the corresponding bits in the <xref linkend="CJAGBHBH">APSR</xref>, <xref linkend="CIHJBHJA">CPSR</xref>, or <xref linkend="CHDDAABB">SPSR</xref>_<current_mode>.</para>
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<para>Because of the Do-Not-Modify nature of its reserved bits, the immediate form of <instruction>MSR</instruction> is normally only useful at the Application level for writing to <value>APSR_nzcvq</value> (<value>CPSR_f</value>).</para>
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<para>If an <instruction>MSR</instruction> (immediate) moves selected bits of an immediate value to the <xref linkend="CIHJBHJA">CPSR</xref>, the PE checks whether the value being written to <xref linkend="BEIDIGBH">PSTATE</xref>.M is legal. See <xref linkend="CHDDFIGE">Illegal changes to PSTATE.M</xref>.</para>
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<para>An <instruction>MSR</instruction> (immediate) executed in User mode:</para>
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<list type="unordered">
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<listitem><content>Is <arm-defined-word>constrained unpredictable</arm-defined-word> if it attempts to update the <xref linkend="CHDDAABB">SPSR</xref>.</content></listitem>
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<listitem><content>Otherwise, does not update any <xref linkend="CIHJBHJA">CPSR</xref> field that is accessible only at EL1 or higher,</content></listitem>
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</list>
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<para>An <instruction>MSR</instruction> (immediate) executed in System mode is <arm-defined-word>constrained unpredictable</arm-defined-word> if it attempts to update the <xref linkend="CHDDAABB">SPSR</xref>.</para>
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<para>The <xref linkend="CIHJBHJA">CPSR</xref>.E bit is writable from any mode using an <instruction>MSR</instruction> instruction. Arm deprecates using this to change its value.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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<para>Related encodings: <xref linkend="A32.encoding_index.movsr_hint_imm">Move Special Register and Hints (immediate)</xref>.</para>
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</encodingnotes>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<iclass name="A1" oneof="1" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="MSR" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/MSR_i/A1_AS.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" name="R" usename="1">
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<c></c>
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</box>
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<box hibit="21" width="2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="mask" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="14" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="13" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="12" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="MSR_i_A1_AS" oneofinclass="1" oneof="1" label="A1" bitdiffs="!(R == 0 && mask == 0000)">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="MSR" />
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</docvars>
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<box hibit="22" width="7" name="R:mask">
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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<c>Z</c>
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</box>
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<asmtemplate><text>MSR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_spec_reg" hover="One of: * {value{APSR_<bits>}}"><spec_reg></a><text>, #</text><a link="sa_imm" hover="Immediate value"><imm></a></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/MSR_i/A1_AS.txt" mylink="aarch32.instrs.MSR_i.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if mask == '0000' && R == '0' then SEE "Related encodings";
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imm32 = <a link="impl-aarch32.A32ExpandImm.1" file="shared_pseudocode.xml" hover="function: bits(32) A32ExpandImm(bits(12) imm12)">A32ExpandImm</a>(imm12); write_spsr = (R == '1');
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if mask == '0000' then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">mask == '0000' && R == '1'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="MSR_i_A1_AS" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MSR_i_A1_AS" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MSR_i_A1_AS" symboldefcount="1">
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<symbol link="sa_spec_reg"><spec_reg></symbol>
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<account encodedin="mask">
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<intro>
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<para>Is one of:</para>
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<list type="unordered">
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<listitem><content><value>APSR_<bits></value>.</content></listitem>
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<listitem><content><value>CPSR_<fields></value>.</content></listitem>
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<listitem><content><value>SPSR_<fields></value>.</content></listitem>
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</list>
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<para>For CPSR and SPSR, <fields> is a sequence of one or more of the following:</para>
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<list type="param">
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<listitem>
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<param>c</param><content>mask<0> = '1' to enable writing of bits<7:0> of the destination PSR.</content>
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</listitem>
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<listitem>
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<param>x</param><content>mask<1> = '1' to enable writing of bits<15:8> of the destination PSR.</content>
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</listitem>
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<listitem>
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<param>s</param><content>mask<2> = '1' to enable writing of bits<23:16> of the destination PSR.</content>
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</listitem>
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<listitem>
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<param>f</param><content>mask<3> = '1' to enable writing of bits<31:24> of the destination PSR.</content>
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</listitem>
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</list>
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<para>For APSR, <bits> is one of <value>nzcvq</value>, <value>g</value>, or <value>nzcvqg</value>. These map to the following CPSR_<fields> values:</para>
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<list type="unordered">
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<listitem><content><value>APSR_nzcvq</value> is the same as <value>CPSR_f</value> (mask== '1000').</content></listitem>
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<listitem><content><value>APSR_g</value> is the same as <value>CPSR_s</value> (mask == '0100').</content></listitem>
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<listitem><content><value>APSR_nzcvqg</value> is the same as <value>CPSR_fs</value> (mask == '1100').</content></listitem>
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</list>
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<para>Arm recommends the <value>APSR_<bits></value> forms when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see <xref linkend="CJAGBHBH">The Application Program Status Register, APSR</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MSR_i_A1_AS" symboldefcount="1">
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<symbol link="sa_imm"><imm></symbol>
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<account encodedin="">
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<intro>
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<para>Is an immediate value. See <xref linkend="BABHDAJF">Modified immediate constants in A32 instructions</xref> for the range of values.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/MSR_i/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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if write_spsr then
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if PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then
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UNPREDICTABLE;
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else
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<a link="impl-aarch32.SPSRWriteByInstr.2" file="shared_pseudocode.xml" hover="function: SPSRWriteByInstr(bits(32) value, bits(4) bytemask)">SPSRWriteByInstr</a>(imm32, mask);
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else
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// Attempts to change to an illegal mode will invoke the Illegal Execution state mechanism
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<a link="impl-aarch32.CPSRWriteByInstr.2" file="shared_pseudocode.xml" hover="function: CPSRWriteByInstr(bits(32) value, bits(4) bytemask)">CPSRWriteByInstr</a>(imm32, mask);</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables ps_block="Operation">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">PSTATE.M IN {M32_User,M32_System} && write_spsr</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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</cu_case>
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</constrained_unpredictables>
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</instructionsection>
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