293 lines
13 KiB
XML
293 lines
13 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
|
|
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
|
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
|
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
|
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
|
|
|
<instructionsection id="MRS" title="MRS -- AArch32" type="instruction">
|
|
<docvars>
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="mnemonic" value="MRS" />
|
|
</docvars>
|
|
<heading>MRS</heading>
|
|
<desc>
|
|
<brief>
|
|
<para>Move Special register to general-purpose register</para>
|
|
</brief>
|
|
<authored>
|
|
<para>Move Special register to general-purpose register moves the value of the <xref linkend="CJAGBHBH">APSR</xref>, <xref linkend="CIHJBHJA">CPSR</xref>, or <xref linkend="CHDDAABB">SPSR</xref>_<current_mode> into a general-purpose register.</para>
|
|
<para>Arm recommends the <value>APSR</value> form when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see <xref linkend="CJAGBHBH">APSR</xref>.</para>
|
|
<para>An <instruction>MRS</instruction> that accesses the <xref linkend="CHDDAABB">SPSRs</xref> is <arm-defined-word>unpredictable</arm-defined-word> if executed in User mode or System mode.</para>
|
|
<para>An <instruction>MRS</instruction> that is executed in User mode and accesses the <xref linkend="CIHJBHJA">CPSR</xref> returns an <arm-defined-word>unknown</arm-defined-word> value for the <xref linkend="CIHJBHJA">CPSR</xref>.{E, A, I, F, M} fields.</para>
|
|
</authored>
|
|
<encodingnotes>
|
|
<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
|
|
</encodingnotes>
|
|
</desc>
|
|
<alias_list howmany="0"></alias_list>
|
|
<classes>
|
|
<classesintro count="2">
|
|
<txt>It has encodings from the following instruction sets:</txt>
|
|
<txt> A32 (</txt>
|
|
<a href="#iclass_a1">A1</a>
|
|
<txt>)</txt>
|
|
<txt> and </txt>
|
|
<txt> T32 (</txt>
|
|
<a href="#iclass_t1">T1</a>
|
|
<txt>)</txt>
|
|
<txt>.</txt>
|
|
</classesintro>
|
|
<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="MRS" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="32" psname="aarch32/instrs/MRS/A1_AS.txt" tworows="1">
|
|
<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
|
|
<c colspan="4">!= 1111</c>
|
|
</box>
|
|
<box hibit="27" width="5" settings="5">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="22" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="21" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="20" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="19" width="4" name="mask" settings="4">
|
|
<c>(1)</c>
|
|
<c>(1)</c>
|
|
<c>(1)</c>
|
|
<c>(1)</c>
|
|
</box>
|
|
<box hibit="15" width="4" name="Rd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="11" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="10" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="9" name="B" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="8" name="m" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="7" width="4" settings="4">
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="3" width="4" name="Rn" settings="4">
|
|
<c>(0)</c>
|
|
<c>(0)</c>
|
|
<c>(0)</c>
|
|
<c>(0)</c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="MRS_A1_AS" oneofinclass="1" oneof="2" label="A1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="A32" />
|
|
<docvar key="mnemonic" value="MRS" />
|
|
</docvars>
|
|
<asmtemplate><text>MRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_spec_reg" hover="Special register to be accessed (field "R") [APSR,CPSR,SPSR]"><spec_reg></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/MRS/A1_AS.txt" mylink="aarch32.instrs.MRS.A1_AS.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); read_spsr = (R == '1');
|
|
if d == 15 then UNPREDICTABLE;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="MRS" />
|
|
</docvars>
|
|
<iclassintro count="1"></iclassintro>
|
|
<regdiagram form="16x2" psname="aarch32/instrs/MRS/T1_AS.txt">
|
|
<box hibit="31" width="11" settings="11">
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>0</c>
|
|
<c>0</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
<c>1</c>
|
|
</box>
|
|
<box hibit="20" name="R" usename="1">
|
|
<c></c>
|
|
</box>
|
|
<box hibit="19" settings="1">
|
|
<c>(1)</c>
|
|
</box>
|
|
<box hibit="18" settings="1">
|
|
<c>(1)</c>
|
|
</box>
|
|
<box hibit="17" settings="1">
|
|
<c>(1)</c>
|
|
</box>
|
|
<box hibit="16" settings="1">
|
|
<c>(1)</c>
|
|
</box>
|
|
<box hibit="15" width="2" settings="2">
|
|
<c>1</c>
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="13" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="12" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="11" width="4" name="Rd" usename="1">
|
|
<c colspan="4"></c>
|
|
</box>
|
|
<box hibit="7" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="6" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="5" settings="1">
|
|
<c>0</c>
|
|
</box>
|
|
<box hibit="4" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="3" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="2" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="1" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
<box hibit="0" settings="1">
|
|
<c>(0)</c>
|
|
</box>
|
|
</regdiagram>
|
|
<encoding name="MRS_T1_AS" oneofinclass="1" oneof="2" label="T1">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="instr-class" value="general" />
|
|
<docvar key="isa" value="T32" />
|
|
<docvar key="mnemonic" value="MRS" />
|
|
</docvars>
|
|
<asmtemplate><text>MRS</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_spec_reg" hover="Special register to be accessed (field "R") [APSR,CPSR,SPSR]"><spec_reg></a></asmtemplate>
|
|
</encoding>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/MRS/T1_AS.txt" mylink="aarch32.instrs.MRS.T1_AS.txt" enclabels="" sections="1" secttype="noheading">
|
|
<pstext mayhavelinks="1" section="Decode" rep_section="decode">d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd); read_spsr = (R == '1');
|
|
if d == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="MRS_A1_AS, MRS_T1_AS" symboldefcount="1">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="MRS_A1_AS, MRS_T1_AS" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="MRS_A1_AS, MRS_T1_AS" symboldefcount="1">
|
|
<symbol link="sa_rd"><Rd></symbol>
|
|
<account encodedin="Rd">
|
|
<intro>
|
|
<para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="MRS_A1_AS, MRS_T1_AS" symboldefcount="1">
|
|
<symbol link="sa_spec_reg"><spec_reg></symbol>
|
|
<definition encodedin="R">
|
|
<intro>Is the special register to be accessed, </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">R</entry>
|
|
<entry class="symbol"><spec_reg></entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">CPSR|APSR</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">SPSR</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/MRS/Op_AS.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
if read_spsr then
|
|
if PSTATE.M IN {<a link="M32_User" file="shared_pseudocode.xml" hover="constant bits(5) M32_User = '10000'">M32_User</a>,<a link="M32_System" file="shared_pseudocode.xml" hover="constant bits(5) M32_System = '11111'">M32_System</a>} then
|
|
UNPREDICTABLE;
|
|
else
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = <a link="impl-shared.SPSR.read.0" file="shared_pseudocode.xml" hover="accessor: bits(N) SPSR[]">SPSR</a>[];
|
|
else
|
|
// CPSR has same bit assignments as SPSR, but with the IT, J, SS, IL, and T bits masked out.
|
|
bits(32) mask = '11111000 11101111 00000011 11011111';
|
|
psr_val = <a link="impl-shared.GetPSRFromPSTATE.2" file="shared_pseudocode.xml" hover="function: bits(N) GetPSRFromPSTATE(ExceptionalOccurrenceTargetState targetELState, integer N)">GetPSRFromPSTATE</a>(<a link="AArch32_NonDebugState" file="shared_pseudocode.xml" hover="enumeration ExceptionalOccurrenceTargetState { AArch32_NonDebugState, AArch64_NonDebugState, DebugState }">AArch32_NonDebugState</a>, 32) AND mask;
|
|
if PSTATE.EL == <a link="EL0" file="shared_pseudocode.xml" hover="constant bits(2) EL0 = '00'">EL0</a> then
|
|
// If accessed from User mode return UNKNOWN values for E, A, I, F bits, bits<9:6>,
|
|
// and for the M field, bits<4:0>
|
|
psr_val<22> = bits(1) UNKNOWN;
|
|
psr_val<9:6> = bits(4) UNKNOWN;
|
|
psr_val<4:0> = bits(5) UNKNOWN;
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[d] = psr_val;</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
<constrained_unpredictables ps_block="Operation">
|
|
<cu_case>
|
|
<cu_cause>
|
|
<pstext mayhavelinks="1">PSTATE.M IN {M32_User, M32_System} && read_spsr</pstext>
|
|
</cu_cause>
|
|
<cu_type constraint="Constraint_UNDEF" />
|
|
<cu_type constraint="Constraint_NOP" />
|
|
</cu_case>
|
|
</constrained_unpredictables>
|
|
</instructionsection>
|