264 lines
14 KiB
XML
264 lines
14 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="MCR" title="MCR -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="MCR" />
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</docvars>
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<heading>MCR</heading>
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<desc>
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<brief>
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<para>Move to System register from general-purpose register or execute a System instruction</para>
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</brief>
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<authored>
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<para>Move to System register from general-purpose register or execute a System instruction. This instruction copies the value of a general-purpose register to a System register, or executes a System instruction.</para>
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<para>The System register and System instruction descriptions identify valid encodings for this instruction. Other encodings are <arm-defined-word>undefined</arm-defined-word>. For more information see <xref linkend="CFIDGFBF">About the AArch32 System register interface</xref> and <xref linkend="BABDFCJB">General behavior of System registers</xref>.</para>
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<para>In an implementation that includes EL2, <instruction>MCR</instruction> accesses to System registers can be trapped to Hyp mode, meaning that an attempt to execute an <instruction>MCR</instruction> instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see <xref linkend="BEIDFAFD">EL2 configurable instruction enables, disables, and traps</xref>.</para>
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<para>Because of the range of possible traps to Hyp mode, the <instruction>MCR</instruction> pseudocode does not show these possible traps.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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<syntaxnotes>
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<para>The possible values of { <syntax><coproc></syntax>, <syntax><opc1></syntax>, <syntax><CRn></syntax>, <syntax><CRm></syntax>, <syntax><opc2></syntax> } encode the entire System register and System instruction encoding space. Not all of this space is allocated, and the System register and System instruction descriptions identify the allocated encodings.</para>
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</syntaxnotes>
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</desc>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="MCR" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/MCR/T1A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="3" name="opc1" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="CRn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="3" name="coproc<3:1>" usename="1" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="8" name="coproc<0>" usename="1">
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<c></c>
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</box>
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<box hibit="7" width="3" name="opc2" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="CRm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="MCR_A1" oneofinclass="1" oneof="2" label="A1">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="MCR" />
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</docvars>
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<asmtemplate><text>MCR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field "coproc<0>") [p14,p15]"><coproc></a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space, in the range 0 to7 (field "opc1")"><opc1></a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, </text><a link="sa_crn" hover="CRn parameter within the System register encoding space [c0-c15] (field "CRn")"><CRn></a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field "CRm")"><CRm></a><text>{</text><text>, </text><a>{#}</a><a link="sa_opc2" hover="Opc2 parameter within the System register encoding space, in the range 0 to7 (field "opc2")"><opc2></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/MCR/T1A1_A.txt" mylink="aarch32.instrs.MCR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); cp = if coproc<0> == '0' then 14 else 15;
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if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="MCR" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/MCR/T1A1_A.txt" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="23" width="3" name="opc1" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="CRn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="3" name="coproc<3:1>" usename="1" settings="3">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="8" name="coproc<0>" usename="1">
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<c></c>
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</box>
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<box hibit="7" width="3" name="opc2" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="CRm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="MCR_T1" oneofinclass="1" oneof="2" label="T1">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="MCR" />
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</docvars>
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<asmtemplate><text>MCR</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_coproc" hover="System register encoding space (field "coproc<0>") [p14,p15]"><coproc></a><text>, </text><a>{#}</a><a link="sa_opc1" hover="Opc1 parameter within the System register encoding space, in the range 0 to7 (field "opc1")"><opc1></a><text>, </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, </text><a link="sa_crn" hover="CRn parameter within the System register encoding space [c0-c15] (field "CRn")"><CRn></a><text>, </text><a link="sa_crm" hover="CRm parameter within the System register encoding space [c0-c15] (field "CRm")"><CRm></a><text>{</text><text>, </text><a>{#}</a><a link="sa_opc2" hover="Opc2 parameter within the System register encoding space, in the range 0 to7 (field "opc2")"><opc2></a><text>}</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/MCR/T1A1_A.txt" mylink="aarch32.instrs.MCR.T1A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); cp = if coproc<0> == '0' then 14 else 15;
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if t == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
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<symbol link="sa_coproc"><coproc></symbol>
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<definition encodedin="coproc<0>">
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<intro>Is the System register encoding space, </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">coproc<0></entry>
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<entry class="symbol"><coproc></entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">p14</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">p15</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
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<symbol link="sa_opc1"><opc1></symbol>
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<account encodedin="opc1">
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<intro>
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<para>Is the opc1 parameter within the System register encoding space, in the range 0 to7, encoded in the "opc1" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
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<symbol link="sa_rt"><Rt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
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<symbol link="sa_crn"><CRn></symbol>
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<account encodedin="CRn">
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<intro>
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<para>Is the CRn parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRn" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
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<symbol link="sa_crm"><CRm></symbol>
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<account encodedin="CRm">
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<intro>
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<para>Is the CRm parameter within the System register encoding space, in the range c0 to c15, encoded in the "CRm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="MCR_A1, MCR_T1" symboldefcount="1">
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<symbol link="sa_opc2"><opc2></symbol>
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<account encodedin="opc2">
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<intro>
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<para>Is the opc2 parameter within the System register encoding space, in the range 0 to7, encoded in the "opc2" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/MCR/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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<a link="AArch32.SysRegWrite.3" file="shared_pseudocode.xml" hover="function: AArch32.SysRegWrite(integer cp_num, bits(32) instr, integer t)">AArch32.SysRegWrite</a>(cp, <a link="impl-shared.ThisInstr.0" file="shared_pseudocode.xml" hover="function: bits(32) ThisInstr()">ThisInstr</a>(), t);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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