263 lines
14 KiB
XML
263 lines
14 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="LSL_MOV_rr" title="LSL (register) -- AArch32" type="alias">
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<docvars>
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<docvar key="alias_mnemonic" value="LSL" />
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="MOV" />
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</docvars>
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<heading>LSL (register)</heading>
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<desc>
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<brief>Logical Shift Left (register)</brief>
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<longer> shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register</longer>
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</desc>
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<aliasto refiform="mov_rr.xml" iformid="MOV_rr">MOV, MOVS (register-shifted register)</aliasto>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t2">T2</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="3" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="5" settings="5">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="22" width="2" name="opc" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="20" name="S" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" settings="4">
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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<c>(0)</c>
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</box>
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<box hibit="15" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="Rs" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" settings="1">
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<c>0</c>
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</box>
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<box hibit="6" width="2" name="stype" usename="1" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="LSL_MOV_rr_A1" oneofinclass="1" oneof="3" label="Not flag setting">
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<docvars>
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<docvar key="alias_mnemonic" value="LSL" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="cond-setting" value="no-s" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="MOV" />
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</docvars>
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<asmtemplate><text>LSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field "Rm")"><Rm></a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="mov_rr.xml#MOV_rr_A1">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field "Rm")"><Rm></a><text>, LSL </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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<iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="MOV" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16" psname="" tworows="1">
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<box hibit="31" width="6" settings="6">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="25" width="4" name="op" usename="1" settings="4">
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="21" width="3" name="Rs" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="18" width="3" name="Rdm" usename="1">
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<c colspan="3"></c>
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</box>
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</regdiagram>
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<encoding name="LSL_MOV_rr_T1_LSL" oneofinclass="1" oneof="3" label="Logical shift left">
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<docvars>
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<docvar key="alias_mnemonic" value="LSL" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="MOV" />
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<docvar key="mnemonic-shift-type" value="MOV-lsl" />
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<docvar key="shift-type" value="lsl" />
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</docvars>
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<asmtemplate comment="Inside IT block"><text>LSL</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>,</text><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="mov_rr.xml#MOV_rr_T1_LSL">MOV</a><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, </text><a link="sa_rdm_1" hover="First general-purpose source register and the destination register (field "Rdm")"><Rdm></a><text>, LSL </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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<aliascond><a link="impl-aarch32.InITBlock.0" file="shared_pseudocode.xml" hover="function: boolean InITBlock()">InITBlock</a>()</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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<iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="22" width="2" name="stype" usename="1" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" name="S" usename="1" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="11" width="4" name="Rd" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="4" settings="4">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="3" width="4" name="Rs" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="LSL_MOV_rr_T2" oneofinclass="1" oneof="3" label="Not flag setting">
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<docvars>
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<docvar key="alias_mnemonic" value="LSL" />
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<docvar key="armarmheading" value="T2" />
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<docvar key="cond-setting" value="no-s" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="MOV" />
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</docvars>
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<asmtemplate comment="Inside IT block, and <Rd>, <Rm>, <shift>, <Rs> can be represented in T1"><text>LSL</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>.W </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field "Rm")"><Rm></a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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<asmtemplate><text>LSL</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><text>{</text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>,</text><text>}</text><text> </text><a link="sa_rm_1" hover="First general-purpose source register (field "Rm")"><Rm></a><text>, </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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<equivalent_to>
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<asmtemplate><a href="mov_rr.xml#MOV_rr_T2">MOV</a><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rd" hover="General-purpose destination register (field "Rd")"><Rd></a><text>, </text><a link="sa_rm_1" hover="First general-purpose source register (field "Rm")"><Rm></a><text>, LSL </text><a link="sa_rs_1" hover="Second general-purpose source register holding a shift amount in its bottom 8 bits (field "Rs")"><Rs></a></asmtemplate>
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<aliascond>Unconditionally</aliascond>
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</equivalent_to>
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</encoding>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="LSL_MOV_rr_A1, LSL_MOV_rr_T1_LSL, LSL_MOV_rr_T2" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LSL_MOV_rr_A1, LSL_MOV_rr_T1_LSL, LSL_MOV_rr_T2" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LSL_MOV_rr_T1_LSL" symboldefcount="1">
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<symbol link="sa_rdm_1"><Rdm></symbol>
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<account encodedin="Rdm">
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<intro>
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<para>Is the first general-purpose source register and the destination register, encoded in the "Rdm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LSL_MOV_rr_A1, LSL_MOV_rr_T2" symboldefcount="1">
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<symbol link="sa_rd"><Rd></symbol>
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<account encodedin="Rd">
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<intro>
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<para>Is the general-purpose destination register, encoded in the "Rd" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LSL_MOV_rr_A1, LSL_MOV_rr_T2" symboldefcount="1">
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<symbol link="sa_rm_1"><Rm></symbol>
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<account encodedin="Rm">
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<intro>
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<para>Is the first general-purpose source register, encoded in the "Rm" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LSL_MOV_rr_A1, LSL_MOV_rr_T1_LSL, LSL_MOV_rr_T2" symboldefcount="1">
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<symbol link="sa_rs_1"><Rs></symbol>
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<account encodedin="Rs">
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<intro>
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<para>Is the second general-purpose source register holding a shift amount in its bottom 8 bits, encoded in the "Rs" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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</instructionsection>
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