417 lines
24 KiB
XML
417 lines
24 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="LDRSH_r" title="LDRSH (register) -- AArch32" type="instruction">
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<docvars>
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="LDRSH" />
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</docvars>
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<heading>LDRSH (register)</heading>
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<desc>
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<brief>
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<para>Load Register Signed Halfword (register)</para>
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</brief>
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<authored>
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<para>Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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<para>Related instructions: <xref linkend="T32.encoding_index.ldst_signed_reg">Load/store, signed (register offset)</xref>.</para>
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</encodingnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="3">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt> and </txt>
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<a href="#iclass_t2">T2</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="3" id="iclass_a1" no_encodings="3" isa="A32">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="LDRSH" />
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</docvars>
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<iclassintro count="3"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/LDRSH_r/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1">
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<c></c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" settings="1">
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<c>0</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="o1" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="10" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="9" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="8" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="7" settings="1">
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<c>1</c>
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</box>
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<box hibit="6" width="2" name="op2" settings="2">
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="LDRSH_r_A1_off" oneofinclass="3" oneof="5" label="Offset" bitdiffs="P == 1 && W == 0">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="address-offset" value="signed-offset" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="LDRSH" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field "Rn")"><Rn></a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field "Rm")"><Rm></a><text>]</text></asmtemplate>
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</encoding>
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<encoding name="LDRSH_r_A1_post" oneofinclass="3" oneof="5" label="Post-indexed" bitdiffs="P == 0 && W == 0">
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<docvars>
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<docvar key="address-form" value="post-indexed" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="LDRSH" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>0</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>0</c>
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</box>
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<asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field "Rn")"><Rn></a><text>], </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field "Rm")"><Rm></a></asmtemplate>
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</encoding>
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<encoding name="LDRSH_r_A1_pre" oneofinclass="3" oneof="5" label="Pre-indexed" bitdiffs="P == 1 && W == 1">
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<docvars>
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<docvar key="address-form" value="pre-indexed" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="LDRSH" />
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</docvars>
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<box hibit="24" width="1" name="P">
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<c>1</c>
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</box>
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<box hibit="21" width="1" name="W">
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<c>1</c>
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</box>
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<asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn_1" hover="General-purpose base register (field "Rn")"><Rn></a><text>, </text><a link="sa__plusminus_" hover="Specifies the index register is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_rm" hover="General-purpose index register (field "Rm")"><Rm></a><text>]!</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/LDRSH_r/A1_A.txt" mylink="aarch32.instrs.LDRSH_r.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '0' && W == '1' then SEE "LDRSHT";
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t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
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(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);
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if t == 15 || m == 15 then UNPREDICTABLE;
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if wback && (n == 15 || n == t) then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">wback && n == t</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is <arm-defined-word>unknown</arm-defined-word>. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="3" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="LDRSH" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16" psname="aarch32/instrs/LDRSH_r/T1_A.txt">
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<box hibit="31" width="4" settings="4">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="27" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="26" name="B" settings="1">
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<c>1</c>
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</box>
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<box hibit="25" name="H" settings="1">
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<c>1</c>
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</box>
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<box hibit="24" width="3" name="Rm" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="21" width="3" name="Rn" usename="1">
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<c colspan="3"></c>
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</box>
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<box hibit="18" width="3" name="Rt" usename="1">
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<c colspan="3"></c>
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</box>
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</regdiagram>
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<encoding name="LDRSH_r_T1" oneofinclass="1" oneof="5" label="T1">
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<docvars>
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<docvar key="address-form" value="base-plus-offset" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="LDRSH" />
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</docvars>
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<asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field "Rm")"><Rm></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/LDRSH_r/T1_A.txt" mylink="aarch32.instrs.LDRSH_r.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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index = TRUE; add = TRUE; wback = FALSE;
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(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, 0);</pstext>
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</ps>
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</ps_section>
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</iclass>
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<iclass name="T2" oneof="3" id="iclass_t2" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="address-form" value="register-offset" />
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="LDRSH" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/LDRSH_r/T2_A.txt" tworows="1">
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<box hibit="31" width="9" settings="9">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="22" width="2" name="size" settings="2">
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<c>0</c>
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<c>1</c>
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</box>
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<box hibit="20" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="11" width="6" settings="6">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="5" width="2" name="imm2" usename="1">
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<c colspan="2"></c>
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</box>
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<box hibit="3" width="4" name="Rm" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="LDRSH_r_T2" oneofinclass="1" oneof="5" label="T2">
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<docvars>
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<docvar key="address-form" value="register-offset" />
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<docvar key="armarmheading" value="T2" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="LDRSH" />
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</docvars>
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<asmtemplate comment="<Rt>, <Rn>, <Rm> can be represented in T1"><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>.W </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field "Rm")"><Rm></a><text>]</text></asmtemplate>
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<asmtemplate><text>LDRSH</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [</text><a link="sa_rn" hover="General-purpose base register (field "Rn")"><Rn></a><text>, </text><a link="sa__plus_" hover="Specifies the index register is added to the base register">{+}</a><a link="sa_rm" hover="General-purpose index register (field "Rm")"><Rm></a><text>{</text><text>, LSL #</text><a link="sa_imm" hover="If present, the size of left shift to apply to the value from {syntax{<Rm>}}, in the range 1-3"><imm></a><text>}</text><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/LDRSH_r/T2_A.txt" mylink="aarch32.instrs.LDRSH_r.T2_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rn == '1111' then SEE "LDRSH (literal)";
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if Rt == '1111' then SEE "Related instructions";
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t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn); m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
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index = TRUE; add = TRUE; wback = FALSE;
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(shift_t, shift_n) = (<a link="SRType_LSL" file="shared_pseudocode.xml" hover="enumeration SRType {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX}">SRType_LSL</a>, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm2));
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if m == 15 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
|
|
</ps_section>
|
|
</iclass>
|
|
</classes>
|
|
<explanations scope="all">
|
|
<explanation enclist="LDRSH_r_A1_off, LDRSH_r_T1, LDRSH_r_T2" symboldefcount="1">
|
|
<symbol link="sa_c"><c></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="LDRSH_r_A1_off, LDRSH_r_T1, LDRSH_r_T2" symboldefcount="1">
|
|
<symbol link="sa_q"><q></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="LDRSH_r_A1_off, LDRSH_r_T1, LDRSH_r_T2" symboldefcount="1">
|
|
<symbol link="sa_rt"><Rt></symbol>
|
|
<account encodedin="Rt">
|
|
<intro>
|
|
<para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="LDRSH_r_A1_off" symboldefcount="1">
|
|
<symbol link="sa_rn_1"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<docvars>
|
|
<docvar key="address-form" value="base-plus-offset" />
|
|
<docvar key="address-offset" value="signed-offset" />
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be used in the offset variant.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="LDRSH_r_T1, LDRSH_r_T2" symboldefcount="2">
|
|
<symbol link="sa_rn"><Rn></symbol>
|
|
<account encodedin="Rn">
|
|
<docvars>
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1 and T2: is the general-purpose base register, encoded in the "Rn" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="LDRSH_r_A1_off" symboldefcount="1">
|
|
<symbol link="sa__plusminus_">+/-</symbol>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the index register is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="LDRSH_r_T1, LDRSH_r_T2" symboldefcount="1">
|
|
<symbol link="sa__plus_">+</symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>Specifies the index register is added to the base register.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="LDRSH_r_A1_off, LDRSH_r_T1, LDRSH_r_T2" symboldefcount="1">
|
|
<symbol link="sa_rm"><Rm></symbol>
|
|
<account encodedin="Rm">
|
|
<intro>
|
|
<para>Is the general-purpose index register, encoded in the "Rm" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="LDRSH_r_T2" symboldefcount="1">
|
|
<symbol link="sa_imm"><imm></symbol>
|
|
<account encodedin="">
|
|
<intro>
|
|
<para>If present, the size of the left shift to apply to the value from <syntax><Rm></syntax>, in the range 1-3. <syntax><imm></syntax> is encoded in imm2. If absent, no shift is specified and imm2 is encoded as <binarynumber>0b00</binarynumber>.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/LDRSH_r/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
offset = <a link="impl-aarch32.Shift.4" file="shared_pseudocode.xml" hover="function: bits(N) Shift(bits(N) value, SRType srtype, integer amount, bit carry_in)">Shift</a>(<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[m], shift_t, shift_n, PSTATE.C);
|
|
offset_addr = if add then (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] + offset) else (<a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n] - offset);
|
|
address = if index then offset_addr else <a link="impl-aarch32.R.read.1" file="shared_pseudocode.xml" hover="accessor: bits(32) R[integer n]">R</a>[n];
|
|
data = <a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,2];
|
|
if wback then <a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[n] = offset_addr;
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(data, 32);</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|