409 lines
23 KiB
XML
409 lines
23 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="LDRD_l" title="LDRD (literal) -- AArch32" type="instruction">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="LDRD" />
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</docvars>
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<heading>LDRD (literal)</heading>
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<desc>
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<brief>
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<para>Load Register Dual (literal)</para>
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</brief>
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<authored>
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<para>Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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<para>Related encodings: <xref linkend="T32.encoding_index.dstd">Load/Store dual, Load/Store-Exclusive, Load-Acquire/Store-Release, table branch</xref>.</para>
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</encodingnotes>
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<syntaxnotes>
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<para>The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
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</syntaxnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="LDRD" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/LDRD_l/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" settings="1">
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<c>(1)</c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" name="W" settings="1">
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<c>(0)</c>
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</box>
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<box hibit="20" name="o1" settings="1">
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<c>0</c>
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</box>
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<box hibit="19" width="4" name="Rn" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="imm4H" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" settings="1">
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<c>1</c>
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</box>
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<box hibit="6" width="2" name="op2" settings="2">
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="4" settings="1">
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<c>1</c>
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</box>
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<box hibit="3" width="4" name="imm4L" usename="1">
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<c colspan="4"></c>
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</box>
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</regdiagram>
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<encoding name="LDRD_l_A1" oneofinclass="1" oneof="2" label="A1">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="LDRD" />
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</docvars>
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<asmtemplate comment="Normal form"><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field "Rt")"><Rt></a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred"><Rt2></a><text>, </text><a link="sa_label_1" hover="The label of literal data item that is to be loaded into {syntax{<Rt>}}"><label></a></asmtemplate>
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<asmtemplate comment="Alternative form"><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt_1" hover="First general-purpose register to be transferred (field "Rt")"><Rt></a><text>, </text><a link="sa_rt2_1" hover="Second general-purpose register to be transferred"><Rt2></a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_1" hover="8-bit unsigned immediate byte offset [0-255] (field "imm4H:imm4L")"><imm></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/LDRD_l/A1_A.txt" mylink="aarch32.instrs.LDRD_l.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rt<0> == '1' then UNPREDICTABLE;
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t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); t2 = t+1; imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm4H:imm4L, 32); add = (U == '1');
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if t2 == 15 then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">Rt<0> == '1'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_ADDITIONAL_DECODE">
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<cu_type_variable name="pseudocode" value="t<0> = '0';" />
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</cu_type>
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<cu_type constraint="Constraint_ADDITIONAL_DECODE">
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<cu_type_variable name="pseudocode" value="t2 = t;" />
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</cu_type>
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<cu_type>
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<cu_type_text>The instruction executes as described, with no change to its behavior and no additional side-effects. This does not apply when Rt == '1111'.</cu_type_text>
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</cu_type>
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">P == '0' || W == '1'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type>
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<cu_type_text>The instruction executes as if P == 1 and W == 0.'</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="LDRD" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/LDRD_l/T1_A.txt">
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<box hibit="31" width="7" settings="7">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1">
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<c></c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="4" name="Rt2" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="7" width="8" name="imm8" usename="1">
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<c colspan="8"></c>
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</box>
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</regdiagram>
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<encoding name="LDRD_l_T1" oneofinclass="1" oneof="2" label="T1" bitdiffs="!(P == 0 && W == 0)">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="LDRD" />
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</docvars>
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<box hibit="24" width="4" name="P:W">
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<c>Z</c>
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<c>Z</c>
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</box>
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<asmtemplate comment="Normal form"><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field "Rt")"><Rt></a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field "Rt2")"><Rt2></a><text>, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{<Rt>}}"><label></a></asmtemplate>
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<asmtemplate comment="Alternative form"><text>LDRD</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="First general-purpose register to be transferred (field "Rt")"><Rt></a><text>, </text><a link="sa_rt2" hover="Second general-purpose register to be transferred (field "Rt2")"><Rt2></a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="Optional 8-bit unsigned immediate byte offset [0-255], default 0 (field "imm8")"><imm></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/LDRD_l/T1_A.txt" mylink="aarch32.instrs.LDRD_l.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '0' && W == '0' then SEE "Related encodings";
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t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); t2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt2);
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imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm8:'00', 32); add = (U == '1');
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if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE; // Armv8-A removes UNPREDICTABLE for R13
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if W == '1' then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="T1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">t == t2</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_LDUNKNOWN" />
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</cu_case>
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">W == '1'</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_WBSUPPRESS" />
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<cu_type>
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<cu_type_text>The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="LDRD_l_A1, LDRD_l_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRD_l_A1, LDRD_l_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRD_l_A1" symboldefcount="1">
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<symbol link="sa_rt_1"><Rt></symbol>
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<account encodedin="Rt">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field. This register must be even-numbered and not R14.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRD_l_T1" symboldefcount="2">
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<symbol link="sa_rt"><Rt></symbol>
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<account encodedin="Rt">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRD_l_A1" symboldefcount="1">
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<symbol link="sa_rt2_1"><Rt2></symbol>
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<account encodedin="">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: is the second general-purpose register to be transferred. This register must be <syntax><R(t+1)></syntax>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRD_l_T1" symboldefcount="2">
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<symbol link="sa_rt2"><Rt2></symbol>
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<account encodedin="Rt2">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRD_l_A1" symboldefcount="1">
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<symbol link="sa_label_1"><label></symbol>
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<account encodedin="imm4H:imm4L">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: the label of the literal data item that is to be loaded into <syntax><Rt></syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Any value in the range -255 to 255 is permitted.</para>
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<para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1. If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRD_l_T1" symboldefcount="2">
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<symbol link="sa_label"><label></symbol>
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<account encodedin="imm8">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: the label of the literal data item that is to be loaded into <syntax><Rt></syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Permitted values of the offset are multiples of 4 in the range -1020 to 1020.</para>
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<para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1.</para>
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<para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRD_l_A1, LDRD_l_T1" symboldefcount="1">
|
|
<symbol link="sa__plusminus_">+/-</symbol>
|
|
<definition encodedin="U">
|
|
<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
|
|
<table class="valuetable">
|
|
<tgroup cols="2">
|
|
<thead>
|
|
<row>
|
|
<entry class="bitfield">U</entry>
|
|
<entry class="symbol">+/-</entry>
|
|
</row>
|
|
</thead>
|
|
<tbody>
|
|
<row>
|
|
<entry class="bitfield">0</entry>
|
|
<entry class="symbol">-</entry>
|
|
</row>
|
|
<row>
|
|
<entry class="bitfield">1</entry>
|
|
<entry class="symbol">+</entry>
|
|
</row>
|
|
</tbody>
|
|
</tgroup>
|
|
</table>
|
|
</definition>
|
|
</explanation>
|
|
<explanation enclist="LDRD_l_A1" symboldefcount="1">
|
|
<symbol link="sa_imm_1"><imm></symbol>
|
|
<account encodedin="imm4H:imm4L">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="A1" />
|
|
<docvar key="isa" value="A32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding A1: is the 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 if omitted, and encoded in the "imm4H:imm4L" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
<explanation enclist="LDRD_l_T1" symboldefcount="2">
|
|
<symbol link="sa_imm"><imm></symbol>
|
|
<account encodedin="imm8">
|
|
<docvars>
|
|
<docvar key="armarmheading" value="T1" />
|
|
<docvar key="isa" value="T32" />
|
|
</docvars>
|
|
<intro>
|
|
<para>For encoding T1: is the optional 8-bit unsigned immediate byte offset, in the range 0 to 255, defaulting to 0 and encoded in the "imm8" field.</para>
|
|
</intro>
|
|
</account>
|
|
</explanation>
|
|
</explanations>
|
|
<ps_section howmany="1">
|
|
<ps name="aarch32/instrs/LDRD_l/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
|
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
|
|
EncodingSpecificOperations();
|
|
address = if add then (<a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) + imm32) else (<a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4) - imm32);
|
|
if <a link="impl-shared.IsAligned.2" file="shared_pseudocode.xml" hover="function: boolean IsAligned(integer x, integer y)">IsAligned</a>(address, 8) then
|
|
data = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,8];
|
|
if <a link="impl-shared.BigEndian.1" file="shared_pseudocode.xml" hover="function: boolean BigEndian(AccessType acctype)">BigEndian</a>(<a link="AccessType_GPR" file="shared_pseudocode.xml" hover="enumeration AccessType { AccessType_IFETCH, AccessType_GPR, AccessType_ASIMD, AccessType_SVE, AccessType_SME, AccessType_IC, AccessType_DC, AccessType_DCZero, AccessType_AT, AccessType_NV2, AccessType_SPE, AccessType_GCS, AccessType_TRBE, AccessType_GPTW, AccessType_TTW }">AccessType_GPR</a>) then
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data<63:32>;
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = data<31:0>;
|
|
else
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = data<31:0>;
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = data<63:32>;
|
|
else
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address,4];
|
|
<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t2] = <a link="impl-aarch32.MemA.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemA[bits(32) address, integer size]">MemA</a>[address+4,4];</pstext>
|
|
</ps>
|
|
</ps_section>
|
|
</instructionsection>
|