287 lines
16 KiB
XML
287 lines
16 KiB
XML
<?xml version="1.0" encoding="utf-8"?>
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<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
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<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
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<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
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<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
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<instructionsection id="LDRB_l" title="LDRB (literal) -- AArch32" type="instruction">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="instr-class" value="general" />
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<docvar key="mnemonic" value="LDRB" />
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</docvars>
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<heading>LDRB (literal)</heading>
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<desc>
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<brief>
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<para>Load Register Byte (literal)</para>
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</brief>
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<authored>
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<para>Load Register Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see <xref linkend="Chddjfjf">Memory accesses</xref>.</para>
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</authored>
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<encodingnotes>
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<para>For more information about the <arm-defined-word>constrained unpredictable</arm-defined-word> behavior of this instruction, see <xref linkend="CJAEGDJC">Architectural Constraints on UNPREDICTABLE behaviors</xref>.</para>
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</encodingnotes>
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<syntaxnotes>
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<para>The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see <xref linkend="BABGCIBA">Use of labels in UAL instruction syntax</xref>.</para>
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</syntaxnotes>
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</desc>
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<operationalnotes>
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<para>If CPSR.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</para>
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</operationalnotes>
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<alias_list howmany="0"></alias_list>
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<classes>
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<classesintro count="2">
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<txt>It has encodings from the following instruction sets:</txt>
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<txt> A32 (</txt>
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<a href="#iclass_a1">A1</a>
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<txt>)</txt>
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<txt> and </txt>
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<txt> T32 (</txt>
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<a href="#iclass_t1">T1</a>
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<txt>)</txt>
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<txt>.</txt>
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</classesintro>
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<iclass name="A1" oneof="2" id="iclass_a1" no_encodings="1" isa="A32">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="LDRB" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="32" psname="aarch32/instrs/LDRB_l/A1_A.txt" tworows="1">
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<box hibit="31" width="4" name="cond" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="27" width="3" settings="3">
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<c>0</c>
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<c>1</c>
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<c>0</c>
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</box>
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<box hibit="24" name="P" usename="1">
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<c></c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" name="o2" settings="1">
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<c>1</c>
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</box>
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<box hibit="21" name="W" usename="1">
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<c></c>
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</box>
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<box hibit="20" name="o1" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" name="Rn" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1">
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<c colspan="4"></c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="LDRB_l_A1" oneofinclass="1" oneof="2" label="A1" bitdiffs="!(P == 0 && W == 1)">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="armarmheading" value="A1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="A32" />
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<docvar key="mnemonic" value="LDRB" />
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</docvars>
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<box hibit="24" width="4" name="P:W">
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<c>Z</c>
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<c>N</c>
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</box>
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<asmtemplate comment="Normal form"><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{<Rt>}}"><label></a></asmtemplate>
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<asmtemplate comment="Alternative form"><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm_1" hover="12-bit unsigned immediate byte offset [0-4095] (field "imm12")"><imm></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/LDRB_l/A1_A.txt" mylink="aarch32.instrs.LDRB_l.A1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if P == '0' && W == '1' then SEE "LDRBT";
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t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32);
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add = (U == '1'); wback = (P == '0') || (W == '1');
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if t == 15 || wback then UNPREDICTABLE;</pstext>
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</ps>
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</ps_section>
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<constrained_unpredictables encoding="A1" ps_block="Decode">
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<cu_case>
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<cu_cause>
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<pstext mayhavelinks="1">wback</pstext>
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</cu_cause>
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<cu_type constraint="Constraint_UNDEF" />
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<cu_type constraint="Constraint_NOP" />
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<cu_type constraint="Constraint_ADDITIONAL_DECODE">
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<cu_type_variable name="pseudocode" value="wback = FALSE;" />
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</cu_type>
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<cu_type>
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<cu_type_text>The instruction treats bit[24] as the P bit, and bit[21] as the writeback (W) bit, and uses the same addressing mode as described in <xref linkend="A32T32-base.instructions.LDRB_i">LDRB (immediate)</xref>. The instruction uses post-indexed addressing when P == '0' and uses pre-indexed addressing otherwise. The instruction is handled as described in <xref linkend="CEGHJGEF">Using R15</xref>.</cu_type_text>
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</cu_type>
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</cu_case>
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</constrained_unpredictables>
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</iclass>
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<iclass name="T1" oneof="2" id="iclass_t1" no_encodings="1" isa="T32">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="LDRB" />
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</docvars>
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<iclassintro count="1"></iclassintro>
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<regdiagram form="16x2" psname="aarch32/instrs/LDRB_l/T1_A.txt" tworows="1">
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<box hibit="31" width="8" settings="8">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>0</c>
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="23" name="U" usename="1">
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<c></c>
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</box>
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<box hibit="22" width="2" name="size" settings="2">
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<c>0</c>
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<c>0</c>
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</box>
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<box hibit="20" name="L" settings="1">
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<c>1</c>
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</box>
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<box hibit="19" width="4" settings="4">
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<c>1</c>
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<c>1</c>
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<c>1</c>
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<c>1</c>
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</box>
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<box hibit="15" width="4" name="Rt" usename="1" settings="4" constraint="!= 1111">
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<c colspan="4">!= 1111</c>
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</box>
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<box hibit="11" width="12" name="imm12" usename="1">
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<c colspan="12"></c>
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</box>
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</regdiagram>
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<encoding name="LDRB_l_T1" oneofinclass="1" oneof="2" label="T1">
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<docvars>
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<docvar key="address-form" value="literal" />
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<docvar key="armarmheading" value="T1" />
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<docvar key="instr-class" value="general" />
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<docvar key="isa" value="T32" />
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<docvar key="mnemonic" value="LDRB" />
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</docvars>
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<asmtemplate comment="Preferred syntax"><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, </text><a link="sa_label" hover="The label of literal data item that is to be loaded into {syntax{<Rt>}}"><label></a></asmtemplate>
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<asmtemplate comment="Alternative syntax"><text>LDRB</text><text>{</text><a link="sa_c" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><c></a><text>}</text><text>{</text><a link="sa_q" hover="See {xref{ARMARM_Babbefhf}{Standard assembler syntax fields}}"><q></a><text>}</text><text> </text><a link="sa_rt" hover="General-purpose register to be transferred (field "Rt")"><Rt></a><text>, [PC, #</text><a link="sa__plusminus_" hover="Specifies the offset is added to or subtracted from the base register (field "U") [+,-]">{+/-}</a><a link="sa_imm" hover="12-bit unsigned immediate byte offset [0-4095] (field "imm12")"><imm></a><text>]</text></asmtemplate>
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</encoding>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/LDRB_l/T1_A.txt" mylink="aarch32.instrs.LDRB_l.T1_A.txt" enclabels="" sections="1" secttype="noheading">
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<pstext mayhavelinks="1" section="Decode" rep_section="decode">if Rt == '1111' then SEE "PLD";
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t = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rt); imm32 = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, 32); add = (U == '1');
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// Armv8-A removes UNPREDICTABLE for R13</pstext>
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</ps>
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</ps_section>
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</iclass>
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</classes>
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<explanations scope="all">
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<explanation enclist="LDRB_l_A1, LDRB_l_T1" symboldefcount="1">
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<symbol link="sa_c"><c></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRB_l_A1, LDRB_l_T1" symboldefcount="1">
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<symbol link="sa_q"><q></symbol>
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<account encodedin="">
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<intro>
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<para>See <xref linkend="Babbefhf">Standard assembler syntax fields</xref>.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRB_l_A1, LDRB_l_T1" symboldefcount="1">
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<symbol link="sa_rt"><Rt></symbol>
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<account encodedin="Rt">
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<intro>
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<para>Is the general-purpose register to be transferred, encoded in the "Rt" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRB_l_A1, LDRB_l_T1" symboldefcount="1">
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<symbol link="sa_label"><label></symbol>
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<account encodedin="imm12">
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<intro>
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<para>The label of the literal data item that is to be loaded into <syntax><Rt></syntax>. The assembler calculates the required value of the offset from the <function>Align(PC, 4)</function> value of the instruction to this label. Permitted values of the offset are -4095 to 4095.</para>
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<para>If the offset is zero or positive, <field>imm32</field> is equal to the offset and <field>add</field> == <enumvalue>TRUE</enumvalue>, encoded as U == 1.</para>
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<para>If the offset is negative, <field>imm32</field> is equal to minus the offset and <field>add</field> == <enumvalue>FALSE</enumvalue>, encoded as U == 0.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRB_l_A1, LDRB_l_T1" symboldefcount="1">
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<symbol link="sa__plusminus_">+/-</symbol>
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<definition encodedin="U">
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<intro>Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and </intro>
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<table class="valuetable">
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<tgroup cols="2">
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<thead>
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<row>
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<entry class="bitfield">U</entry>
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<entry class="symbol">+/-</entry>
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</row>
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</thead>
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<tbody>
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<row>
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<entry class="bitfield">0</entry>
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<entry class="symbol">-</entry>
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</row>
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<row>
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<entry class="bitfield">1</entry>
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<entry class="symbol">+</entry>
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</row>
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</tbody>
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</tgroup>
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</table>
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</definition>
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</explanation>
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<explanation enclist="LDRB_l_A1" symboldefcount="1">
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<symbol link="sa_imm_1"><imm></symbol>
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<account encodedin="imm12">
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<docvars>
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<docvar key="armarmheading" value="A1" />
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<docvar key="isa" value="A32" />
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</docvars>
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<intro>
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<para>For encoding A1: is the 12-bit unsigned immediate byte offset, in the range 0 to 4095, defaulting to 0 if omitted, and encoded in the "imm12" field.</para>
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</intro>
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</account>
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</explanation>
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<explanation enclist="LDRB_l_T1" symboldefcount="2">
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<symbol link="sa_imm"><imm></symbol>
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<account encodedin="imm12">
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<docvars>
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<docvar key="armarmheading" value="T1" />
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<docvar key="isa" value="T32" />
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</docvars>
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<intro>
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<para>For encoding T1: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the "imm12" field.</para>
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</intro>
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</account>
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</explanation>
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</explanations>
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<ps_section howmany="1">
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<ps name="aarch32/instrs/LDRB_l/Op_A.txt" mylink="execute" enclabels="" sections="1" secttype="Operation">
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<pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="impl-aarch32.ConditionPassed.0" file="shared_pseudocode.xml" hover="function: boolean ConditionPassed()">ConditionPassed</a>() then
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EncodingSpecificOperations();
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base = <a link="impl-shared.Align.2" file="shared_pseudocode.xml" hover="function: integer Align(integer x, integer y)">Align</a>(<a link="impl-aarch32.PC.read.none" file="shared_pseudocode.xml" hover="accessor: bits(32) PC">PC</a>,4);
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address = if add then (base + imm32) else (base - imm32);
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<a link="impl-aarch32.R.write.1" file="shared_pseudocode.xml" hover="accessor: R[integer n] = bits(32) value">R</a>[t] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a link="impl-aarch32.MemU.read.2" file="shared_pseudocode.xml" hover="accessor: bits(8*size) MemU[bits(32) address, integer size]">MemU</a>[address,1], 32);</pstext>
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</ps>
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</ps_section>
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</instructionsection>
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